Feasibility of Digital Circuit Design based on Nanoscale Field-Effect Bipolar Junction Transistor

Shokri, A.; Amirmazlaghani, M.

doi:10.22061/jecei.2022.8287.503

فهرست نشریات

دانشگاه تربیت دبیر شهید رجائی

انتشارات دانشگاه تربیت دبیر شهید رجائی

نشریات مستقل دانشگاه در سامانه ارزیابی نشریات علمی وزارت علوم

نشریه معماری وشهرسازی پایدار موفق به اخذ رتبه علمی-پژوهشی شد

تعداد نشریات	11
تعداد شماره‌ها	210
تعداد مقالات	2,098
تعداد مشاهده مقاله	2,877,837
تعداد دریافت فایل اصل مقاله	2,085,712

	Feasibility of Digital Circuit Design based on Nanoscale Field-Effect Bipolar Junction Transistor
Journal of Electrical and Computer Engineering Innovations (JECEI)
مقاله 23، دوره 11، شماره 1، فروردین 2023، صفحه 33-40 اصل مقاله (981.68 K)
نوع مقاله: Original Research Paper
شناسه دیجیتال (DOI): 10.22061/jecei.2022.8287.503
نویسندگان
A. Shokri؛ M. Amirmazlaghani^*
Electrical Engineering Department, Shahid Rajaee Teacher Training University, Tehran, Iran.
تاریخ دریافت: 19 دی 1400، تاریخ بازنگری: 14 اردیبهشت 1401، تاریخ پذیرش: 24 اردیبهشت 1401
چکیده
Background and Objectives: The Field-effect Bipolar Junction Transistor (FEBJT) is a device with a bipolar junction transistor (BJT) characteristics except that it is designed with standard CMOS technology. Therefore, it can be implemented in nanometer dimensions without the usual restrictions in fabricating the nanoscale BJTs. In addition to the advantages that FEBJT has as a bipolar junction transistor in analog circuits, it can also be used to design digital circuits. Here, we have investigated the capability of FEBJT as the base of a new digital family in nanometer scales. Methods: To do this, we have designed and simulated an inverter logic gate based on FEBJT. We have presented this logic gate's static and dynamic assessment criteria and compared these characteristics with other technologies. Also, a three-stage ring oscillator circuit based on FEBJT is designed and presented. A three-dimensional TCAD Mixed-Mode simulator has been used for the simulations. Results: The value of maximum frequency, PDP, dynamic power, and ring frequency are calculated 0.25THz, 38×10-17 J, 94uW, and 85GHz, respectively. Conclusion: The excellent function of the FEBJT-based inverter gate and oscillator demonstrates that this device can be used as the base of new digital circuits and can open a doorway to the nanoscale CMOS digital family.
کلیدواژه‌ها
Digital circuits؛ BJT؛ FET؛ Inverter logic gate؛ Nanoscale

مراجع
[1] J. N. Bureghartz, “Guide to State-of-the-art Electron Devices,” John Wiley & Sons, 2013. [2] K. Washio, “SiGe HBT and BiCMOS technologies for optical transmission and wireless communication systems,” IEEE Trans. Electron devices, 50(3): 656-668, 2003. [3] S. Athanasiou, C. A. Legrand, S. Cristoloveanu, P. Galy, “Novel ultrathin FD-SOI BIMOS device with reconfigurable operation,” IEEE Trans. Electron Devices, 64(3): 916-922, 2017. [4] J.H. Seo, K. Zhang, M. Kim, W. Zhou, Z. Ma, “High-performance flexible BiCMOS electronics based on single-crystal Si nanomembrane,” NPJ Flexible Electron., 1(1): 1-7, 2017. [5] J. Cai, T. H. Ning, “Bipolar transistors on thin SOI: concept, status and prospect,” in Proc. 7th International Conference on Solid-State and Integrated Circuits Technology, 3: 2102-2107, 2004. [6] K. Nadda, M. J. Kumar, “Vertical bipolar charge plasma transistor with buried metal layer,” Sci. Rep., 5, 7860, 2015. [7] S. Raman, P. Sharma, T. G. NeoGi, M. R. Leroy, R. Clark, J. F. McDonald, “On the performance of lateral SiGe heterojunction bipolar transistors with partially depleted base,” IEEE Trans. Electron Devices, 62(8): 2377-2383, 2015. [8] F. Bashir, S. A. Loan, M. Nizamuddin, H. Shabir, A. M. Murshid, M. Rafat, A. R. Alamoud, S. A. Abbasi, “A novel high performance nanoscaled dopingless lateral PNP transistor on silicon on insulator,” in proc. IMECS, 2014. [9] A. Sahu, L. K. Bramhane, J. Singh, “Symmetric lateral doping-free BJT: a novel design for mixed signal applications,” IEEE Trans. Electron Devices, 63(7): 2684-2690, 2016. [10] P. Agnihotri, P. Dhakras, J. U. Lee, “Bipolar junction transistors in two-dimensional WSe2 with large current and photocurrent gains,” Nano lett., 16(7): 4355-4360, 2016. [11] P. Chevalier, F. Gianesello, A. Pallotta, J. A. Goncalves, G. Bertrand, J. Borrel, L. Boissonnet, E. Brezza, M. Buczko, E. Canderle, D. Celi, “PD-SOI CMOS and SiGe BiCMOS technologies for 5G and 6G communications,” in Proc. 2020 IEEE International Electron Devices Meeting (IEDM): 34-4, 2020. [12] E. Preisler, “A commercial foundry perspective of SiGe BiCMOS process technologies,” in Prpc. 2020 IEEE BiCMOS and Compound Semiconductor Integrated Circuits and Technology Symposium (BCICTS): 1-5, 2020. [13] P. Chevalier, F. Gianesello, A. Pallotta, J. A. Goncalves, G. Bertrand, J. Borrel, L. Boissonnet, E. Brezza, M. Buczko, E. Canderle, D. Celi, “PD-SOI CMOS and SiGe BiCMOS Technologies for 5G and 6G communications,” in Proc. 2020 IEEE International Electron Devices Meeting (IEDM): 34-4, 2020. [14] L. Bramhane, S. Salankar, M. Gaikwad, M. Panchore, “Impact of work function engineering in charge plasma based bipolar devices,” Silicon, 14: 3993-3997, 2022. [15] A. Sahu, A. Kumar, S. P. Tiwari, “Exploration of logic gates and multiplexer using doping-free bipolar junction transistor,” Solid-State Electron., 180, 107994, 2021. [16] S. Zafar, M. A. Raushan, S. Ahmad, M. J. Siddiqui, “Reducing off-state leakage current in dopingless transistor employing dual metal drain,” Semicond. Sci. Technol., 35(1): 015016, 2019. [17] F. Raissi, M. Amirmazlaghani and A. Rajabi, “Field-effect BJT: an adaptive and multifunctional nanoscale transistor,” Appl. Nanosci., 1-13, 2022. [18] M. Amirmazlaghani, A. Rajabi, “New design of bipolar transistor with field-effect doping,” in Proc. KBEI2017, Science and Technology university, 20DEC, 2017. [19] F. Raissi, “A brief analysis of the field-effectdiode and breakdown transistor,” IEEE Trans. Electron Devices, 43(2): 362-365, 1996. [20] F. Raissi, M. Amirmazlaghani, A. Rajabi, "A multifunctional sub-10nm transistor," arXiv preprint arXiv:2108.00297, 2021. [21] Q. Zhao, W. Sun, J. Zhao, L. Feng, X. Xu, W. Liu, X. Guo, Y. Liu, H. Yang, “Noise margin, delay, and power model for pseudo-CMOS TFT logic circuits,” IEEE Trans. Electron Devices, 64(6): 2635-2642, 2017. [22] S.H.C. Baek, K. W. Park, D. S. Kil, Y. Jang, J. Park, K. J. Lee, B. G. Park, “Complementary logic operation based on electric-field controlled spin–orbit torques,” Nat. Electron., 1(7): 398-403, 2018. [23] H. Elgabra, A. Siddiqui, S. Singh, “Design and simulation of a novel bipolar digital logic technology for a balanced performance in 4H-SiC,” IEEE Electron Device Lett., 37(3): 257-260, 2016. [24] A. Siddiqui, H. Elgabra, S. Singh, “Design considerations for 4H-SiC lateral BJTs for high temperature logic applications,” IEEE J. Electron Devices Soc., 6: 126-134, 2017. [25] X. Gao, C. Sui, S. Hemmady, J. Rivera, S. J. Yakura, D. Pommerenke, A. Patnaik, D. G. Beetner, “Modeling static delay variations in push–pull CMOS digital logic circuits due to electrical disturbances in the power supply,” IEEE Trans. Electromagn. Compat., 57(5): 1179-1187, 2015. [26] K. Nayak, M. Bajaj, A. Konar, P. J. Oldiges, K. Natori, H. Iwai, K. V. Murali, V. R. Rao, “CMOS logic device and circuit performance of Si gate all around nanowire MOSFET,” IEEE Trans. Electron Devices, 61(9): 3066-3074, 2014. [27] S. Guin, M. Sil, A. Mallik, “Comparison of logic performance of CMOS circuits implemented with junctionless and inversion-mode FinFETs,” IEEE Trans. Electron Devices, 64(3): 953-959, 2017. [28] T. K. Chiang, “A new device-physics-based noise margin/logic swing model of surrounding-gate MOSFET working on subthreshold logic gate,” IEEE Trans. Electron Devices, 64(1): 306-311, 2016. [29] B. J. Touchaei, N. Manavizadeh, “Design and simulation of low-power logic gates based on nanoscale side-contacted FED,” IEEE Trans. Electron Devices, 64(1): 306-311, 2016. [30] M.A. A. Hafiz, L. Kosuru, M.I. Younis, “Microelectromechanical reprogrammable logic device,” Nat. commun., 7(1): 1-9, 2016. [31] Y. Leblebici, S. M. Kang, “CMOS digital integrated circuits: analysis and design,” McGraw-Hill, 1996. [32] A.L. Zimpeck, C. Meinhardt, R. A. L Reis, “Impact of PVT variability on 20 nm FinFET standard cells,” Microelectron. Reliab., 55(9-10): 1379-1383, 2015. [33] S. Dubey, P. N. Kondekar, “Performance comparison of conventional and strained FinFET inverters,” Microelectron. J, 55: 108-115, 2016. [34] H. Vallabhaneni, A. Japa, S. Shaik, K. S. R. Krishna, R. Vaddi, “Designing energy efficient logic gates with Hetero junction Tunnel fets at 20nm,” in Proc. 2014 2nd International Conference on Devices, Circuits and Systems (ICDCS): 1-5, 2014. [35] U. Mushtaq, V. K. Sharma, “Performance analysis for reliable nanoscaled FinFET logic circuits,” Analog Integr. Circuits Signal Process., 107(3): 671-682, 2021. [36] M.K.Q. Jooq, A. Mir, S. Mirzakuchaki, A. Farmani, “Semi-analytical modeling of high performance nanoscale complementary logic gates utilizing ballistic carbon nanotube transistors,” Physica E, 104: 286-296, 2018. [37] N. Grag, Y. Pratap, M. Gupta, s. Kabra, “Impact of different localized trap charge profiles on the short channel double gate junctionless nanowire transistor based inverter and Ring Oscillator circuit,” AEU Int. J. Electron. Commun., 108: 251-261, 2019. [38] S.K. Shelke, V. N. Nitnaware, S. Rode, “Design of ring oscillator with better temperature, supply voltage & process stability with 32nm FDSOI transistor for ISM band application,” in Proc. 2017 11th International Conference on Intelligent Systems and Control (ISCO): 311-313, 2017. [39] A. Baidya, T. R. Lenka, S. Baishya, “Application of 3D double gate Junctionless transistor for ring oscillator,” in Proc. 2016 International Conference on Recent Advances and Innovations in Engineering (ICRAIE): 1-4, 2016. [40] S. Salem, M. Tajabadi, M. Saneei, “The design and analysis of dual control voltages delay cell for low power and wide tuning range ring oscillators in 65 nm CMOS technology for CDR applications,” AEU Int. J. Electron. Commun., 82: 406-412, 2017. [41] M. Abou Chahine, H. Bazzi, A. Mohsen, A. Harb, A. Kassem, “A low-noise voltage-controlled ring oscillator in 28-nm FDSOI technology for UWB applications,” AEU Int. J. Electron. Commun., 97: 94-101, 2018. [42] J.C. Chien, P. Upadhyaya, H. Jung, S. Chen, W. Fang, A. M. Niknejad, J. Savoj, K. Chang, “2.8 A pulse-position-modulation phase-noise-reduction technique for a 2-to-16GHz injection-locked ring oscillator in 20nm CMOS,” in Proc. 2014 IEEE International Solid-State Circuits Conference Digest of Technical Papers (ISSCC): 52-53, 2014. [43] P. K. Pal, B. K. Kaushik, S. Dasgupta, “Investigation of symmetric dual-k spacer trigate FinFETs from delay perspective,” IEEE Trans. Electron Devices, 61(11): 3579-3585, 2014. [44] M. R. Tripathy, A. K. Singh, A. Samad, S. Chander, K. Baral, P. K. Singh, S. Jit, “Device and circuit-level assessment of GaSb/Si heterojunction vertical tunnel-FET for low-power applications,” IEEE Trans. Electron Devices, 67(3): 1285-1292, 2020. [45] S. Seifollahi, S. A. S. Ziabari, A. Kiani-sarkaleh, “A design of nanoscale double-gate FET based ring oscillator with improved oscillation frequency using device engineering,” AEU Int. J. Electron. Commun., 134, 153701, 2021. [46] H. Lu, P. Paletti, W. Li, P. Fay, T. Ytterdal, A. Seabaugh, “Tunnel FET analog benchmarking and circuit design,” IEEE J. Explor. Solid-State Comput. Devices Circuits, 4(1): 19-25, 2018. [47] M.Y. Kao, G. Pahwa, A. Dasgupta, S. Salahuddin, C. Hu, “Analysis and modeling of polarization gradient effect on negative capacitance FET,” IEEE Trans. Electron Devices, 67(10): 4521-4525, 2020.
آمار تعداد مشاهده مقاله: 523 تعداد دریافت فایل اصل مقاله: 409

سامانه مدیریت نشریات علمی. طراحی و پیاده سازی از سیناوب

پیوندهای مفید

پیوندهای مفید

اخبار و اعلانات

آمار

Feasibility of Digital Circuit Design based on Nanoscale Field-Effect Bipolar Junction Transistor