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Soltani Farani, B., Dorosti, H., Salehi, M., Fakhraie, Si M.. (1398). Ultra-Low-Energy DSP Processor Design for Many-Core Parallel Applications. فناوری آموزش, 8(1), 71-84. doi: 10.22061/jecei.2020.6969.350
B. Soltani Farani; H. Dorosti; M. E. Salehi; Si M. Fakhraie. "Ultra-Low-Energy DSP Processor Design for Many-Core Parallel Applications". فناوری آموزش, 8, 1, 1398, 71-84. doi: 10.22061/jecei.2020.6969.350
Soltani Farani, B., Dorosti, H., Salehi, M., Fakhraie, Si M.. (1398). 'Ultra-Low-Energy DSP Processor Design for Many-Core Parallel Applications', فناوری آموزش, 8(1), pp. 71-84. doi: 10.22061/jecei.2020.6969.350
Soltani Farani, B., Dorosti, H., Salehi, M., Fakhraie, Si M.. Ultra-Low-Energy DSP Processor Design for Many-Core Parallel Applications. فناوری آموزش, 1398; 8(1): 71-84. doi: 10.22061/jecei.2020.6969.350

Ultra-Low-Energy DSP Processor Design for Many-Core Parallel Applications

Journal of Electrical and Computer Engineering Innovations (JECEI)
دوره 8، شماره 1، فروردین 2020، صفحه 71-84    اصل مقاله (1.71 M)
نوع مقاله: Original Research Paper
شناسه دیجیتال (DOI): 10.22061/jecei.2020.6969.350
نویسندگان
B. Soltani Farani1؛ H. Dorosti2؛ M. E. Salehi* 1؛ Si M. Fakhraie1
1Electrical and Computer Engineering Department, University of Tehran, Tehran, Iran
2Computer Engineering Department, Shahid Rajaee Teacher Training University, Tehran, Iran.
تاریخ دریافت: 15 بهمن 1397،  تاریخ بازنگری: 10 خرداد 1398،  تاریخ پذیرش: 10 آذر 1398 
چکیده
Background and Objectives: Digital signal processors are widely used in energy constrained applications in which battery lifetime is a critical concern. Accordingly, designing ultra-low-energy processors is a major concern. In this work and in the first step, we propose a sub-threshold DSP processor.
Methods: As our baseline architecture, we use a modified version of an existing ultra-low-power general purpose processor. Afterwards, we make some modifications to add new instructions to the processor instruction set for better adapting to signal processing applications. In the second step, employing sub-threshold cores in many-core architectures, we use the proposed processor as simple basic cores in a many-core architecture.
Results: In comparison with the baseline architecture, these modifications reduce the program memory size about 42% in average. In addition, data memory accesses are reduced about 60% in average, and more than 90% speed-up is achieved. According to the improvements in total execution time (93%) and power consumption (27%), the total consumed energy is reduced about 95% in average with at most 2.6% area overhead and without increasing the process variation effects on processor specifications.
Conclusion: The results show that for parallel applications, such as FFT in LTE standard, exploiting sub-threshold processors in a many-core architecture not only can satisfy the required performance, but also reduce the power consumption about 50% or even more.
کلیدواژه‌ها
DSP processor؛ Ultra-low-energy؛ Sub-threshold circuits؛ Many-core architectures
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