دانشگاه تربیت دبیر شهید رجائی
انتشارات دانشگاه تربیت دبیر شهید رجائی

  اخبار و اعلانات

 آمار

تعداد نشریات11
تعداد شماره‌ها208
تعداد مقالات2,090
تعداد مشاهده مقاله2,830,793
تعداد دریافت فایل اصل مقاله2,050,381
Mouri Zadeh Khaki, A., Farshidi, E., Ansari Asl, K.. (1398). A Novel Low-Power FPGA-based 1-1 MASH ΔΣ Time-to-Digital Converter Employing one Counter for both Stages. فناوری آموزش, 7(2), 173-182. doi: 10.22061/jecei.2020.6673.333
A. Mouri Zadeh Khaki; E. Farshidi; K. Ansari Asl. "A Novel Low-Power FPGA-based 1-1 MASH ΔΣ Time-to-Digital Converter Employing one Counter for both Stages". فناوری آموزش, 7, 2, 1398, 173-182. doi: 10.22061/jecei.2020.6673.333
Mouri Zadeh Khaki, A., Farshidi, E., Ansari Asl, K.. (1398). 'A Novel Low-Power FPGA-based 1-1 MASH ΔΣ Time-to-Digital Converter Employing one Counter for both Stages', فناوری آموزش, 7(2), pp. 173-182. doi: 10.22061/jecei.2020.6673.333
Mouri Zadeh Khaki, A., Farshidi, E., Ansari Asl, K.. A Novel Low-Power FPGA-based 1-1 MASH ΔΣ Time-to-Digital Converter Employing one Counter for both Stages. فناوری آموزش, 1398; 7(2): 173-182. doi: 10.22061/jecei.2020.6673.333

A Novel Low-Power FPGA-based 1-1 MASH ΔΣ Time-to-Digital Converter Employing one Counter for both Stages

Journal of Electrical and Computer Engineering Innovations (JECEI)
مقاله 5، دوره 7، شماره 2، مهر 2019، صفحه 173-182    اصل مقاله (1.31 M)
نوع مقاله: Original Research Paper
شناسه دیجیتال (DOI): 10.22061/jecei.2020.6673.333
نویسندگان
A. Mouri Zadeh Khaki1؛ E. Farshidi* 1، 2؛ K. Ansari Asl1، 2
1Department of Electrical Engineering, Mahshahr Branch, Islamic Azad University, Mahshahr, Iran.
2Department of Electrical Engineering, Faculty of Engineering, Shahid Chamran University of Ahvaz, Ahvaz, Iran.
تاریخ دریافت: 27 تیر 1397،  تاریخ بازنگری: 09 اسفند 1397،  تاریخ پذیرش: 09 خرداد 1398 
چکیده
Background and Objectives: Beside acceptable performance, power consumption and chip area are important issues in embedded systems that should be taken into consideration.
Methods: In this paper, a novel continuous-time 1-1 MASH ∆∑ Time-to-digital converter (TDC) is presented. Since the proposed design utilizes 12-bit quantizer based on Gated Switched-Ring Oscillator (GSRO) for both stages, it has been implemented all-digitally. By using a novel structure, only one multi-bit counter is employed for both stages, therefore the required hardware for implementation of this work is much less than conventional TDCs. As a result, complexity, chip area and power consumption would decrease considerably.
Results: We implemented the proposed design prototype on an Altera Stratix IV FPGA board. Measured results demonstrate that although this work uses less complex architecture in comparison with previous works, it provides appropriate performance such as 60.7 dB SNR within 8 MHz signal bandwidth at 400 MHz sampling rate while consuming 2.79 mW.
Conclusion: Experimental results reveals suitability of the proposed TDC to be incorporated in fast and accurate applications such as ADPLLs and high-resolution photoacoustic tomography. Also, by adjusting the proposed novel structure with more stages higher order of noise-shaping can be attained to enhance SNR and time-resolution further.
کلیدواژه‌ها
Delta-sigma modulation؛ Gated Switched-Ring Oscillator (GSRO)؛ Multi-stage-noise-shaping (MASH)؛ Oversampling؛ Voltage-Controlled Oscillator (VCO)
مراجع

[1] M. R. Nasiriavanaki et al., “High-resolution photoacoustic tomography of resting-state functional connectivity in the mouse brain,” PNAS, 111(1): 21–26, 2014.

[2] V. Nguyen, D. Duong, Y. Chung, J.W. Lee, “A Cyclic Vernier Two-Step TDC for High Input Range Time-of-Flight Sensor Using Startup Time Correction Technique,” Sensors, 18(11): 3948,  2018.

[3] A. Hussein, S. Vasadi, J. Paramesh, “A 50–66-GHz Phase-Domain Digital Frequency Synthesizer with Low Phase Noise and Low Fractional Spurs,” IEEE J. Solid State Circuits, 52(12): 3329–3347, 2017.

[4] S. Mahdavi, “A 12 bit 76MS/s SAR ADC with a Capacitor Merged Technique in 0.18µm CMOS Technology,” J. Elec. Comput. Eng. Innov., 5(2): 121-130, 2017.

[5] N. Yan, L. Ma, Y. Xu, S. Chen, X. Liu, J. Xiang, H. Min, “A Low Power All-Digital PLL With -40dBc In-Band Fractional Spur Suppression for NB-IoT Applications,” IEEE Access, 7): 7897-7904, 2018.

[6] P. Lu, Y. Wu, P. Andreani, “A 2.2-ps Two-Dimensional Gated-Vernier Time-to-Digital Converter with Digital Calibration,” IEEE Trans. Circuits Syst. II Express Briefs, 63(11): 1019–1023, 2016.

[7] W. Yu et al., “A time-domain high-order MASH ADC using voltage-controlled gated-ring oscillator,” IEEE Trans. Circuits Syst. I, Reg. Papers, 60, No.4): 856–866, 2013.

[8] J. S. Kim et al., “A 300-MS/s, 1.76-ps-resolution, 10-b asynchronous pipelined time-to-digital converter with on-chip digital background calibration in 0.13-m CMOS,” IEEE J. Solid-State Circuits, 48(2): 516–526, 2013.

[9] K.S. Kim et al., “A 7 bit, 3.75 ps resolution two-step time-to-digital converter in 65 nm CMOS using pulse-train time amplifier,” IEEE J. Solid-State Circuits, 48(4): 1009-1017, 2013.

[10] K.S. Kim et al., “A 9 b, 1.12 ps resolution 2.5 b/stage pipelined time-to-digital converter in 65 nm CMOS using time-register,” IEEE J. Solid-State Circuits, 49, No.4): 1007–1016, 2014.

[11] Y. H. Seo et al., “A 1.25 ps resolution 8 b cyclic TDC in 0.13 CMOS,” IEEE J. Solid-State Circuits, 47(3): 736–743, 2012.

[12] H. Chung et al., “A 10-Bit 80-MS/s decision-select successive approximation TDC in 65 nm CMOS,” IEEE J. Solid-State Circuits, 47(5): 1232–1241, 2012.

[13] S. Samadigorji, B. Zakeri, M. R. Zahabi, “A-New-Closed-form-Mathematical-Approach-to-Achieve Minimum Phase Noise in Frequency Synthesizers,” J. Elec. Comput. Eng. Innov., 2(1): 7-13, 2014.

[14] M. Gande et al., “A 71 dB dynamic range third-order TDC using charge-pump,” in Proc. IEEE Symp. on VLSI Circuits (VLSIC), Honolulu, HI, USA, 2012.

[15] B. Young et al., “A 2.4 ps resolution 2.1 mW second-order noiseshaped time-to-digital converter with 3.2 ns range in 1 MHz bandwidth,” in Proc. IEEE custom integrated circuits conference (CICC), San Jose, CA, USA, 2010.

[16] M. Z. Straayer et al., “A multi-path gated ring oscillator TDC with first-order noise shaping,” IEEE J. Solid-State Circuits, 44(4): 1089–1098, 2009.

[17] A. Elshazly et al., “A 13 b 315 fsrms 2 mW 500 MS/s 1 MHz bandwidth highly digital time-to-digital converter using switched ring oscillators,” in Proc. IEEE Int. Solid-State Circuits Conf. Dig. Tech. Papers, San Francisco, CA, USA, 2012.

[18] T. Konishi et al., “A 61-dB SNDR 700 second-order all-digital TDC with low-jitter frequency shift oscillator and dynamic flipflops,” in Proc. IEEE Symp. on VLSI Circuits (VLSIC) Dig. Tech. Papers, Honolulu, HI, USA, 2012.

[19] W. Yu, K. S. Kim, S. H. Cho, “A 148 fsrms integrated noise 4 MHz bandwidth second-order ∆∑ time-to-digital converter with gated switched-ring oscillator,” IEEE Trans. Circuits Syst. I, Reg. Papers, 61(8): 2281–2289, 2014.

[20] W. Yu, J. W. Kim, K. S. Kim, S. H. Cho, “A Time-domain High-order MASH ∆∑ ADC using Voltage-Controlled Gated-Ring Oscillator,” IEEE Trans. Circuits Syst. I, Reg. Papers, 60(4): 856–866, 2013.

[21] W. Yu, K. S. Kim, S. H. Cho, “A 0.22 psrms Integrated Noise 15 MHz Bandwidth Fourth-Order ΔΣ Time-to-Digital Converter Using Time-Domain Error-Feedback Filter,” IEEE Journal of solid-state circuits, 50(5): 1251–1262, 2015.

[22] A. Mouri Zadeh Khaki, E. Farshidi, S. H. MD Ali, M. Othman, “An FPGA-Based 16-Bit Continuous-Time 1-1 MASH ∆∑ TDC Employing Multirating Technique,” Electronics MDPI, 8(11): 1285, 2019.

[23] S.T. Chandrasekaran, A. Jayaraj, M. Danesh, A. Sanyal, “A Highly Digital Second-Order Oversampling TDC,” IEEE Solid State Circuits Letters, 1(5): 114–117, 2018.

[24] Q. Liu, A. Edward, D. Zhou, J. Silva-Martinez, “A Continuous-Time MASH 1-1-1 Delta–Sigma Modulator with FIR DAC and Encoder-Embedded Loop-Unrolling Quantizer in 40-nm CMOS,” IEEE Trans. Very Large Scale Integr. (VLSI) Syst., 26(4): 756–767, 2018.

[25] M.B. Dayanik, D. Weyer, M.P. Flynn, “A 5GS/s 156MHz BW 70dB DR continuous-time sigma-delta modulator with time-interleaved reference data-weighted averaging,” In Proc. Symposium on VLSI Circuits (VLSIC), Kyoto, Japan, 2017.

[26] A. Edward, Q. Liu, C. Briseno-Vidrios, M. Kinyua, E.G. Soenen, A.I. Karşılayan, J. Silva-Martinez, “A 43-mW MASH 2-2 CT PD Modulator Attaining 74.4/75.8/76.8 dB of SNDR/SNR/DR and 50 MHz of BW in 40-nm CMOS,” IEEE J. Solid State Circuits, 52(2): 448–459, 2017.

[27] H. Li, L. Breyne, J. Van Kerrebrouck, M. Verplaetse, C.Y. Wu, P. Demeester, G. Torfs, “A 21-GS/s Single-Bit Second-Order Delta–Sigma Modulator for FPGAs,” IEEE Trans. Circuits Syst. II Express Briefs, 66(3): 482–486, 2019.

[28] M. Z. Straayer, “Noise shaping techniques for analog and time to digital converters using voltage controlled oscillators,” Ph.D. dissertation, MIT, Cambridge, 2008.

[29] J. Kim et al., “Analysis and design of voltage-controlled oscillator based analog-to-digital converter,” IEEE Trans. Circuits Syst. I, Reg. Papers, 57(1): 18–30, 2010.

آمار
تعداد مشاهده مقاله: 610
تعداد دریافت فایل اصل مقاله: 495


سامانه مدیریت نشریات علمی. طراحی و پیاده سازی از سیناوب