| Journal of Electrical and Computer Engineering Innovations (JECEI) | ||
| Article 2, Volume 2, Issue 1 - Serial Number 3, January 0, Pages 7-13 PDF (406.89 K) | ||
| DOI: 10.22061/jecei.2014.37 | ||
| Receive Date: 20 October 2013, Revise Date: 15 December 2013, Accept Date: 15 December 2013 | ||
| References | ||
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[1] B. Razavi, “RF Microelectronics,” 2nd ed, Prentice-Hall, 2011, p. 638.
[2] P. EnSu, S. Pamarti, “Fractional‐N Phase‐Locked‐Loop‐Based Frequency Synthesis: A Tutorial,” IEEE Trans. Circuits and Systems—II: Express Briefs, Vol. 56, No. 12, pp. 881—885, December 2009.
[3] Y. W. Kim, and J. D. Yu, “Phase Noise Model of Single Loop Frequency Synthesizer,” IEEE Trans. on Broadcasting, vol. 54, NO. 1, pp. 112‐119, March. 2008.
[4] X. Yan, X. Kuang, and N. Wu, “An Accurate and Fast Behavioral Model for PLL Frequency Synthesizer Phase Noise/Spurs Prediction,” IEEE Custom Integrated Circuits Conference, pp. M‐ 17‐1—M‐17‐4, Sept. 2009.
[5] A. Hajimiri, “Noise in Phase‐Locked Loops,” Symp. on MixedSignal Design, pp. 1‐6, Feb. 2001.
[6] F. M. Gardner, “Charge‐Pump Phase‐Locked Loops,”IEEE Trans. Comm., Vol. COM‐28, pp.1849‐1858, November 1980. [7] P. K. Hanumolu, M. Brownlee, K. Mayaram, and U. K. Moon, “Analysis of Charge‐Pump Phase‐Locked Loops,” IEEE Trans. on Circuit and Systems–I, Vol. 51, No. 9, pp. 1665–1674, September 2004.
[8] A. Lacaita, S. Levantino, and C. Samori, “Integrated Frequency Synthesizers for Wireless Systems,” UK: Cambridge, 2007.
[9] A. Holme, “15‐25MHz Fractional‐N Synthesizer,” 2005. [Online]. Available at: http://www.holmea.demon.co.uk/Frac2/Mash.htm.
[10] M.H. Perrott, M.D. Trott, and C.G. Sodini, “A Modeling Approach for Sigma‐Delta Fractional‐N Frequency Synthesizers Allowing Straightforward Noise Analysis,” IEEE J. Solid‐State Circuits, Vol. 37, No. 8, pp. 1028‐‐1038, 2002.
[11] H. C. Luong, G. C. Leung, “LowVoltage CMOS RF Frequency Synthesizers,” Cambridge University Press, 2004. [12] Dean Banerjee, “PLLPerformance, Simulation and Design Handbook,,”(4thEdition), 2008, [online]. Available at:http://ww w.national.com/appinfo/wireless/pll_design book.
[13] A. Hajimiri, T. H. Lee, “A General Theory of Phase Noise in Electrical Oscillators,”IEEE J. SolidState Circuits, Vol. 33, No. 2, pp. 179‐194, Feb. 1998.
[14] D. Ham and A. Hajimiri, “Concepts and Methods in Optimization of Integrated LC VCOs,” IEEE J. SolidState Circuits, Vol. 36, No. 6, June 2001.
[15] J. Craninckx and M. Steyaert, “Low‐noise voltage controlled oscillators using enhanced LC‐tanks,” IEEE Trans. Circ.Syst.II, Vol. 42, pp. 794‐904, Dec. 1995.
[16] S. Norsworthy, R. Schreier, and G. Temes, “Delta‐Sigma DataConverters: Theory, Design, and Simulation,” IEEE Press, 1997.
[17] W. Gao, X. Gao, “Design of PLL frequency synthesizer based on the fourth‐order active filter,” IEEE Conf., ISSSE, International Symposium, Vol. 2, pp. 1‐3, Sept. 2010 | ||
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