An Ultra-low Power Ternary Multi-digit Adder Applies GDI Method for Binary Operations

Ahmadzadeh Khosroshahi, N.; Dehyadegari, M.; Razaghian, F.

doi:10.22061/jecei.2022.9065.570

فهرست نشریات

دانشگاه تربیت دبیر شهید رجائی

انتشارات دانشگاه تربیت دبیر شهید رجائی

نشریات مستقل دانشگاه در سامانه ارزیابی نشریات علمی وزارت علوم

نشریه معماری وشهرسازی پایدار موفق به اخذ رتبه علمی-پژوهشی شد

تعداد نشریات	11
تعداد شماره‌ها	210
تعداد مقالات	2,098
تعداد مشاهده مقاله	2,877,815
تعداد دریافت فایل اصل مقاله	2,085,691

	An Ultra-low Power Ternary Multi-digit Adder Applies GDI Method for Binary Operations
Journal of Electrical and Computer Engineering Innovations (JECEI)
دوره 11، شماره 1، فروردین 2023، صفحه 189-202 اصل مقاله (973.5 K)
نوع مقاله: Original Research Paper
شناسه دیجیتال (DOI): 10.22061/jecei.2022.9065.570
نویسندگان
N. Ahmadzadeh Khosroshahi¹؛ M. Dehyadegari^* ²؛ F. Razaghian¹
¹Department of Electrical Engineering, South Tehran Branch, Islamic Azad University, Tehran, Iran.
²Department of Electrical Engineering, South Tehran Branch, Islamic Azad University, Tehran, Iran & Department of Computer Engineering, K.N. Toosi University of Technology, Tehran, Iran.
تاریخ دریافت: 02 تیر 1401، تاریخ بازنگری: 01 شهریور 1401، تاریخ پذیرش: 15 شهریور 1401
چکیده
Background and Objectives: This paper introduces a novel low-power and low-delay multi-digit ternary adder in carbon nanotube field effect transistor (CNTFET) technology. Methods: In the proposed design, reducing the power consumption is the main priority. In this multi valued logic design, geometry-dependent threshold voltage of the CNTFET is the design code. At each stage, a half adder is applied to generate the intermediate binary signals called half-sum (HS) and half-carry (HC). For the binary operations, the gate diffusion input (GDI) method is used to significantly reduce the power consumption as in the proposed decoder design. Results: In this work a GDI based sum generator and a low-power encoder are used to calculate the final sum value of each stage. Furthermore, the proposed carry generation/propagation block results in a significant reduction in the overall propagation delay time. The simulation reveals a significant improvement in terms of power consumption (up to 27%), PDP (up to 41%) and FO4 delay (up to 20%). Conclusion: A CNTFET based power and delay efficient multi-digit ternary adder has been presented in this paper. The simulation is performed by the Synopsis HSPICE simulator with Stanford 32 nm CNTFET technology. According to the results, a significant saving in average power consumption is achieved where the power-delay product (PDP) is improved by 41% compared to the best existing design.
کلیدواژه‌ها
CNTFET؛ Low power Adder؛ Ternary logic؛ Multi-valued logic؛ GDI

مراجع
[1] M. Rezaei Khezeli, M. H. Moaiyeri, A. Jalali, "Analysis of crosstalk effects for multiwalled carbon nanotube bundle interconnects in ternary logic and comparison with cu interconnects," IEEE Trans. Nanotechnology, 16(1): 107-117, 2017 [2] A. Naeemi, R. Sarvari, J. D. Meindl, "On-Chip interconnect networks at the end of the roadmap: Limits and Nanotechnology opportunities," in Proc. 2006 International Interconnect Technology Conference, 2006. [3] P. C. Balla, A. Antoniou, "Low power dissipation MOS ternary logic family," IEEE J. Solid-State Circuits, 19(5): 739-749, 1984. [4] L. Yu-Ming, J. Appenzeller, J. Knoch, P. Avouris, "High-performance carbon nanotube field-effect transistor with tunable polarities," IEEE Trans. Nanotechnology, 4(5): 481-489, 2005. [5] P. Keshavarzian, R. Sarikhani, “A Novel CNTFET-based ternary full adder,” Circuits Syst. Signal Process., 33: 665–679, 2014. [6] R. Faghih Mirzaee, K. Navi, N. Bagherzadeh, "High-Efficient circuits for ternary addition," VLSI Des., 2014: 534587, 2014. [7] S. K. Sahoo, K. Dhoot, R. Sahoo, "High performance ternary multiplier using CNTFET," 2018 IEEE Computer Society Annual Symposium on VLSI (ISVLSI): 269, 2018. [8] B. Srinivasu, K. Sridharan, "A synthesis methodology for ternary logic circuits in emerging device technologies," IEEE Trans. Circuits Syst I: Regul. Pap., 64(8): 2146-2159, 2017. [9] G. Hills, C. Lau, A. Wright, et al. “Modern microprocessor built from complementary carbon nanotube transistors,” Nature, 572: 595–602, 2019. [10] S. L. Murotiya, A. Gupta, "Design of high speed ternary full adder and three-input XOR circuits using CNTFETs," in Proc. 2015 28th International Conference on VLSI Design, 2015. [11] M. H. Moaiyeri, A. Doostaregan, K. Navi, "Design of energy efficient and robust ternary circuits for nanotechnology," IET Circuits Devices Syst., 5(4): 285-296, 2011. [12] K. Sridharan, S. Gurindagunta, V. Pudi, "Efficient multiternary digit adder design in CNTFET technology," IEEE Trans. Nanotechnology, 12(3): 283-287, 2013. [13] C. Vudadha, S. Katragadda, P. S. Phaneendra, "2:1 Multiplexer based design for ternary logic circuits," in Proc. 2013 IEEE Asia Pacific Conference on Postgraduate Research in Microelectronics and Electronics (PrimeAsia), 2013. [14] B. Srinivasu, K. Sridharan, "Carbon nanotube FET-based low-delay andlow-power multi-digit adder designs," IET Circuits Devices Syst., 11(4): 352-364, 2017. [15] S. L. Murotiya, A. Gupta, “A novel design of ternary full adder using CNTFETs,” Arab J. Sci. Eng., 39: 7839–7846, 2014. [16] C. Vudadha, S. Phaneendra Parlapalli, M. B. Srinivas, “Energy efficient design of CNFET-based multi-digit ternary adders,” Microelectronics J., 75: 75-86, 2018. [17] B. Srinivasu, K. Sridharan, "Low-Complexity multiternary digit multiplier design in CNTFET technology," IEEE Trans. Circuits Systems II: Express Briefs, 63(8): 753-757, 2016. [18] C. Vudadha, M. B. Srinivas, "Design of high-speed and power-efficient ternary prefix adders using CNFETs," IEEE Trans. Nanotechnology, 17(4): 772-782, 2018. [19] C. Vudadha, P. S. Phaneendra, G. Makkena, V. Sreehari, N. M. Muthukrishnan, M. B. Srinivas, "Design of CNFET based ternary comparator using grouping logic," in Proc. 2012 IEEE Faible Tension Faible Consommation, 2012. [20] C. Vudadha, P. S. Phaneendra, M. B. Srinivas, "An efficient design methodology for CNFET Based ternary logic circuits," in Proc. 2016 IEEE International Symposium on Nanoelectronic and Information Systems (iNIS), 2016. [21] N. Ahmadzadeh Khosroshahi, M. Dehyadegari, F. Razaghian, “A high-efficiency Wallace tree based multi-trit multiplier in CNTFET technology,” Int. J. Electron., 1(19): 1244-1257, 2022. [22] S. Lata Murotiya, A. Gupta, “Hardware-efficient low-power 2-bit ternary ALU design in CNTFET technology,” Int. J. Electron., 103(5): 913-927, 2016. [23] S. L. Murotiya, A. Gupta, S. Vasishth, "Novel design of ternary magnitude comparator using CNTFETs," in Proc. 2014 Annual IEEE India Conference (INDICON), 2014. [24] G. Hills et al., "Understanding energy efficiency benefits of carbon nanotube field-effect transistors for digital VLSI," IEEE Trans. Nanotechnology, 17(6): 1259-1269, 2018. [25] Y. Xie, Z. Zhang, D. Zhong et al., “Speeding up carbon nanotube integrated circuits through three-dimensional architecture,” Nano Res., 12: 1810–1816, 2019. [26] A. P. Dhande, V. T. Ingole, " Design and implementation of 2-bit ternary ALU slice," in Proc. Int. Conf. IEEE-Sci. Electron., Technol. Inf. Telecommun: 17-21, 2005. [27] S. Lata Murotiya, A. Gupta, “Design of CNTFET-based 2-bit ternary ALU for nanoelectronics”, Int. J. Electron., 101(9): 1244-1257, 2014. [28] S. Lata Murotiya, A. Gupta, “Hardware-efficient low-power 2-bit ternary ALU design in CNTFET technology”, Int. J. Electron., 103(5): 913- 927, 2016. [29] T. Sharma, L. Kumre, “Energy-Efficient ternary arithmetic logic unit design in CNTFET technology,” Circuits Syst. Signal Process. 39: 3265–3288, 2020. [30] A. Morgenshtein, A. Fish, A. Wagner, "Gate-diffusion input (GDI)-a novel power efficient method for digital circuits: a design methodology," in Proc. 14th Annual IEEE International ASIC/SOC Conference (IEEE Cat. No.01TH8558), 2001. [31] M. Shaveisi, A. Rezaei, “Design and implementation of CNTFET-Based reversible combinational digital circuits using the GDI Technique for ultra-low power applications,” BioNanoSci. 10: 1063–1083, 2020. [32] I. Sutherland, S. Fairbanks, "GasP: a minimal FIFO control," in Proc. Seventh International Symposium on Asynchronous Circuits and Systems. ASYNC 2001, 2001. [33] R. O. Ozdag, P. A. Beerel, "High-speed QDI asynchronous pipelines," in Proc. Eighth International Symposium on Asynchronous Circuits and Systems, 2002. [34] A. Morgenshtein, M. Moreinis, R. Ginosar, "Asynchronous gate-diffusion-input (GDI) circuits," IEEE Trans. Very Large Scale Integr. (VLSI) Syst., 12(8): 847-856, 2004. [35] K. Sridharan, S. Gurindagunta, V. Pudi, "Efficient multiternary digit adder design in CNTFET technology," IEEE Trans. Nanotechnology, 12(3): 283-287, 2013. [36] R. Faghih Mirzaee, K. Navi, N. Bagherzadeh, "High-efficient circuits for ternary addition," VLSI Design, 2014: 534587, 2014. [37] C. Vudadha, S. Phaneendra Parlapalli, M. B. Srinivas, “Energy efficient design of CNFET-based multi-digit ternary adders,” Microelectronics J., 75: 75-86, 2018. [38] S. Lin, Y. Kim, F. Lombardi, "CNTFET-Based design of ternary logic gates and arithmetic circuits," IEEE Trans. Nanotechnology, 10(2): 217-225, 2019. [39] C. Vudadha, P. S. Phaneendra, M. B. Srinivas, "An efficient design methodology for CNFET based ternary logic circuits," in Proc. 2016 IEEE International Symposium on Nanoelectronic and Information Systems (iNIS), 2016. [40] F. Sharifi, M. H. Moaiyeri, K. Navi, N. Bagherzadeh, “Robust and energy-efficient carbon nanotube FET-based MVL gates: A novel design approach”, Microelectronics J., .46(12): Part A, 2015. [41] P. Soleimani Abhari, F. Razaghian, "A novel median based image impulse noise suppression system using spiking neurons on FPGA," Comput. Methods Biomech. Biomed. Eng.: Imaging Visualization, 8(6): 631-640, 2020. [42] P. Soleimani Abhari, F. Razaghian, "Hardware implementation of LIF and HH spiking neuronal models," Signal Process. Renewable Energy, 3(1): 35-42, 2019. [43] P. Soleimani ABHARI, M. Dosaranian Moghadam, "Design and Simulation of a modified 32-bit ROM-based direct digital frequency synthesizer on FPGA," AUT J. Electr. Eng., 47(1): 23-29, 2015. [44] P. Soleimani Abhari, F. Razaghian, S. Talebi Toti, "Single spiking neuron as direct digital frequency synthesizer," Signal Process. Renewable Energy, 3(3): 73-81, 2019. [45] P. Keshavarzian, R. Sarikhani, “A novel CNTFET-based ternary full adder”, Circ. Syst. Signal Process. 33 (3): 665-679, 2014. [46] S.L. Murotiya, A. Gupta, “Design of high speed ternary full adder and three-input XOR circuits using CNTFETs, in Proc. 2015 28th International Conference on VLSI Design, 2015. [47] R. F. Mirzaee, K. Navi, N. Bagherzadeh, “High-efficient circuits for ternary addition”, VLSI Des., 2014: 534587, 2014. [48] S. Rani, Suman, B. Singh, "Cntfet based 4-trit hybrid ternary adder-subtractor for low power & high-speed applications,” Silicon, 14: 689–702, 2022. [49] J. Deng, H. S. P. Wong, “A compact SPICE model forcarbon-nanotube field-effect transistors including nonidealitiesand its application—Part II: Full device model and circuitperformance benchmarking,” IEEE Trans. Electron. Devices, 54(12): 3195–3205, 2007.
آمار تعداد مشاهده مقاله: 489 تعداد دریافت فایل اصل مقاله: 402

سامانه مدیریت نشریات علمی. طراحی و پیاده سازی از سیناوب

پیوندهای مفید

پیوندهای مفید

اخبار و اعلانات

آمار

An Ultra-low Power Ternary Multi-digit Adder Applies GDI Method for Binary Operations