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Shakibaee, F., Bijari, A., Zahiri, S.H.. (1399). Design of a High-Speed and Low Power CMOS Comparator for A/D Converters. فناوری آموزش, 9(2), 153-160. doi: 10.22061/jecei.2021.7602.409
F. Shakibaee; A. Bijari; S.H. Zahiri. "Design of a High-Speed and Low Power CMOS Comparator for A/D Converters". فناوری آموزش, 9, 2, 1399, 153-160. doi: 10.22061/jecei.2021.7602.409
Shakibaee, F., Bijari, A., Zahiri, S.H.. (1399). 'Design of a High-Speed and Low Power CMOS Comparator for A/D Converters', فناوری آموزش, 9(2), pp. 153-160. doi: 10.22061/jecei.2021.7602.409
Shakibaee, F., Bijari, A., Zahiri, S.H.. Design of a High-Speed and Low Power CMOS Comparator for A/D Converters. فناوری آموزش, 1399; 9(2): 153-160. doi: 10.22061/jecei.2021.7602.409

Design of a High-Speed and Low Power CMOS Comparator for A/D Converters

Journal of Electrical and Computer Engineering Innovations (JECEI)
مقاله 3، دوره 9، شماره 2، مهر 2021، صفحه 153-160    اصل مقاله (1000.74 K)
نوع مقاله: Original Research Paper
شناسه دیجیتال (DOI): 10.22061/jecei.2021.7602.409
نویسندگان
F. Shakibaee؛ A. Bijari* ؛ S.H. Zahiri
Department of Electrical Engineering, Faculty of Electrical and Computer Engineering, University of Birjand, Birjand, Iran
تاریخ دریافت: 25 خرداد 1399،  تاریخ بازنگری: 04 آبان 1399،  تاریخ پذیرش: 07 دی 1399 
چکیده
Background and Objectives: Comparators play a critical role in the analog to digital converters (ADCs) and digital to analog converters (DACs). So, different structures have been proposed to improve their performance. Power, delay, offset, and noise are the important factors that have significantly affect the comparator’s performance. In low power applications, power consumption and delay are the critical concerns that should be minimized to obtain better performance. In this work, a low-power and high-speed comparator has been proposed, which is suitable for applications operating at a low power supply.
Methods: Based on the conventional structure of the comparator, some modifications are implemented to achieve better performance in terms of power consumption and delay. Additionally, the proposed structure gives great performance when the difference of inputs is very small. To verify the proposed structure, it is designed and simulated in a 0.18 μm CMOS technology with a power supply of 1 V and sampling frequency of 2 MHz.
Results: To draw a fair comparison, the conventional and proposed structure is simulated in equal circumstance. The size of transistors is designed with appropriate W/L ratios to achieve appropriate performance. The proposed structure not only reduces the power consumption by 44%, but also it decreases the delay by 9.1%. The power consumption of the proposed structure is around 0.12 µw. The total occupied area by the proposed structure is approximately 127.44 µm2.
Conclusion: In this paper, we presented a delay analysis for the proposed dynamic comparator. Also, based on theoretical analyses, a new dynamic comparator consumes less power and operates faster compared with the conventional structure. The simulation results verify the theoretical analysis.

کلیدواژه‌ها
Dynamic comparator؛ High-speed؛ Low-power؛ Bulk driven
مراجع

[1] F. Rabbi, S. Das, Q.D. Hossain, N.S. Pathan, "Design of a low-power ultra-high-speed dynamic latched comparator in 90-nm CMOS technology," in Proc. International IEEE Conference on Computer, Communication, Chemical, Material and Electronic Engineering (IC4ME2): 1-4, 20

[2] M. Gangwar, A. Nishad, “Design and simulation of modified ultra-low power CMOS comparator for sigma delta modulator,” in Proc. The Second International Conference on Intelligent Computing and Control Systems: 1425-1427, 2018.

[3] A. Khorami, M. Baraani Dastjerdi, A. Fotowat Ahmadi, “A low-power high-speed comparator for analog to digital converters,” in Proc. IEEE International Symposium on Circuits and Systems (ISCAS): 2011-2013, 2016.

[4] J. Lu, J. Holleman, “A low-power high-precision comparator with time-domain bulk-tuned offset cancellation,” IEEE Trans. Circuits Syst. I Regul. Pap., 60(5): 1158-1167, 2013.

[5] M. Nasrollahpour, C. Yen, S. Hamedi-hagh, “A high-speed, low-offset and low-power differential comparator for analog to digital converters,” in Proc. International SoC Design Conference (ISOCC): 220-221, 2017.

[6] M. Vaijayanthi, K. Vivek, “Analysis of dynamic comparators in ultra-low supply voltages for high speed ADCs,” presented at the 2nd International Conference on Innovations in Information, Embedded and Communication systems (ICIIECS), Tehran. Iran, 2015.

[7] Y. Ishijima, S. Nakagawa, H. Ishikuro, “Measurement time reduction technique for input referred noise of dynamic comparator,” pesented at the 2018 IEEE International Conference on Microelectronic Test Structures (ICMTS), Austin, TX, 2018.

[8] M.D. Scott, B.E. Boser, K.S.J. Pister, “An ultralow-energy ADC for smart dust,” IEEE J. Solid-State Circuits, 38(7): 1123-1129, 2003.

[9] F. Shakibaee, F. Sajedi, M. Saberi, "Low-power successive approximation ADC using split-monotonic,” IET Circuits Devices Syst., 12: 203-208, 2017.

[10] K. Inoue, T. Matsuura, A. Hyogo, H. San, “Non-binary cyclic and binary SAR hybrid ADC,” presented at the MIXDES - 24th International Conference "Mixed Design of Integrated Circuits and Systems, 2017.

[11] M. Saberi, R. Lotfi, "Segmented architecture for successive approximation analog-to-digital converters," IEEE Trans. Very Large Scale Integr. VLSI Syst., 22: 593-606, 2014.

[12] M. Taherzadeh-Sani, A. Hamoui, “A reconfiguration 10-12b 0.4-44MS/s pipelined ADC in 1.2V 90nm digital CMOS,” in Proc. ESSCIRC: 382-385, 2010.

[13] C .Srikar Datta, G. Prasad, V.S. Prasad Nayak, G. Bhargav, “Design and analysis of a 16-bit 10MHz pipeline ADC in 0.25μ CMOS,” presented at the IEEE International Conference on Computational Intelligence and Computing Research (ICCIC), Madurai, India, 2015.

[14] S. Bakhtar, S. Dalu, “Design and implementation of low power pipeline ADC,” presented at the International Conference on Research in Intelligent and Computing in Engineering (RICE), San Salvador, 2018.

[15] P. Arunkumar, G. Rekha, P. Narashimaraja, “An efficient design of 3bit and 4bit flash ADC,” Int. J. Comput. Appl., 61(11): 32-37, 2013.

[16] A. Inamdar, A. Sahu, J. Ren, S. Setoodeh, R. Mansour, D. Gupta, “Design and evaluation of flash ADC,” IEEE Trans. Appl. Supercond., 25(3): 1-5, 2015.

[17] P. Rahul, A. Kulkarni, S. Sankanur, M. Raghavendra, “Reduced comparators for low power flash ADC using TSMC018,” presented at the International conference on Microelectronic Devices, Circuits and Systems (ICMDCS), Vellore, 2017.

[18] P.M. Figueiredo, J.C. Vital, “Kickback noise reduction techniques for CMOS latched comparators,” IEEE Trans. Circuits Syst., 53(7): 541 – 545, 2006.

[19] M. Aldacher, M. Nasrollahpour, S. Hamedi-hagh, “A low-power, high-resolution, 1 GHz differential comparator with low-offset and low-kickback,” presented at the 2017 24th IEEE International Conference on Electronics, Circuits and Systems (ICECS), Batumi, 2017.

[20] H. Yousefi, S.M. Mirsanei, “Design of a novel high speed and low kick back noise dynamic latch comparator,” presented at the 28th Iranian Conference on Electrical Engineering (ICEE), Iran, 2020.

[21] X. Xin, J. Cai, R. Xie, P. Wang, “Ultra-low power comparator with dynamic offset cancellation for SAR ADC,” Electron. Lett., 53(24): 1572–1574, 2017.

[22] J. F. Gao, G. J. Li, Q. Li, “High-speed low-power common-mode insensitive dynamic comparator,” Electron. Lett., 51(2): 134–136, 2015.

[23] D.G. Xu, S.L. Xu, G.B. Chen, “High-speed low-power and low power supply voltage dynamic comparator,” Electron. Lett., 51(23): 1914–1916, 2015.

[24] B.J. Blalock, “Body-driving as a low-voltage analog design technique for CMOS technology,” in Proc. IEEE Southwest Symp. Mixed-Signal Design: 113–118, 2000.

[25] Z. Huang, H. Zhang, “Low-voltage bulk-drive high-speed comparator for ADCs,” Electron. Lett., 55(13): 735–737, 2019.

[26] M. Maymandi-Nejad, M. Sachdev, “1-bit quantiser with rail to rail input range for sub-1V modulators,” IEEE Electron. Lett., 39: 894–895, 2003.

[27] D. Shinkel, E. Mensink, E. Klumperink, E. van Tuijl, B. Nauta, “A double-tail latch-type voltage sense amplifier with 18ps setup hold time,” in Proc. IEEE Int. Solid-State Circuits Conf., Dig. Tech. Papers: 314–315, 2007.

[28] C.C. Liu, S.J. Chang, G.Y. Huang, “A 10-bit 50-MS/s SAR ADC with a monotonic capacitor switching procedure,” IEEE J. Solid State Circuits, 45(4): 731–740, 2010.

[29] S. Babayan-Mashhadi, R. Lotfi, “Analysis and design of a low voltage low-power double-tail comparator,” IEEE Trans. Very Large Scale Integr. (VLSI) Syst., 22: 343–352, 2014.

[30] H. Aghabeigi, M. Jafaripanah, “High speed low power voltage comparator in 0.18um CMOS process for flash ADC,” in Proc. International Conference on Knowledge-Based Engineering and Innovation: 418-421, 2017.

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