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Shaveisi, M., Rezaei, A.. (1397). Performance Analysis of Reversible Sequential Circuits Based on Carbon NanoTube Field Effect Transistors (CNTFETs). فناوری آموزش, 6(2), 173-183. doi: 10.22061/jecei.2019.5015.183
M. Shaveisi; A. Rezaei. "Performance Analysis of Reversible Sequential Circuits Based on Carbon NanoTube Field Effect Transistors (CNTFETs)". فناوری آموزش, 6, 2, 1397, 173-183. doi: 10.22061/jecei.2019.5015.183
Shaveisi, M., Rezaei, A.. (1397). 'Performance Analysis of Reversible Sequential Circuits Based on Carbon NanoTube Field Effect Transistors (CNTFETs)', فناوری آموزش, 6(2), pp. 173-183. doi: 10.22061/jecei.2019.5015.183
Shaveisi, M., Rezaei, A.. Performance Analysis of Reversible Sequential Circuits Based on Carbon NanoTube Field Effect Transistors (CNTFETs). فناوری آموزش, 1397; 6(2): 173-183. doi: 10.22061/jecei.2019.5015.183

Performance Analysis of Reversible Sequential Circuits Based on Carbon NanoTube Field Effect Transistors (CNTFETs)

Journal of Electrical and Computer Engineering Innovations (JECEI)
مقاله 6، دوره 6، شماره 2، مهر 2018، صفحه 173-183    اصل مقاله (1.59 M)
نوع مقاله: Original Research Paper
شناسه دیجیتال (DOI): 10.22061/jecei.2019.5015.183
نویسندگان
M. Shaveisi* ؛ A. Rezaei
Department of Electrical Engineering, Kermanshah University of Technology, Kermanshah, Iran
تاریخ دریافت: 31 مرداد 1396،  تاریخ بازنگری: 09 اسفند 1396،  تاریخ پذیرش: 09 خرداد 1397 
چکیده
Background and Objectives: This study presents the importance of reversible logic in designing of high performance and low power consumption digital circuits. In our research, the various forms of sequential reversible circuits such as D, T, SR and JK flip-flops are investigated based on carbon nanotube field-effect transistors.
Methods: By simultaneous using of the reversible logic gates and carbon nanotube transistors in implementation of various flip-flops and introducing suitable transistor circuits of conventional reversible gates, all reversible flip-flops are simulated in two voltages, 0.3 and 0.5 Volt. The Hspice_H-2013.03-SP2 software is used to simulate these circuits using the 32nm CNTFET technology (the standard Stanford spice model).
Results: The simulation results indicate a significant reduction in the average power consumption of D, T, SR and JK flip-flops, respectively about 99.98%, 82.79%, 60.46%, and 81.53%.
Conclusion: Our results show that the proposed structures have achieved a high performance in terms of average power consumption and PDP.


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Copyrights
©2018 The author(s). This is an open access article distributed under the terms of the Creative Commons Attribution (CC BY 4.0), which permits unrestricted use, distribution, and reproduction in any medium, as long as the original authors and source are cited. No permission is required from the authors or the publishers.
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کلیدواژه‌ها
Reversible logic؛ Sequential circuit؛ Carbon nanotube field effect transistor؛ Flip-flop؛ Power consumption
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