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Shaveisi, M., Rezaei, A.. (1397). Performance Analysis of Reversible Sequential Circuits Based on Carbon NanoTube Field Effect Transistors (CNTFETs). فناوری آموزش, 6(2), 173-183. doi: 10.22061/jecei.2019.5015.183
M. Shaveisi; A. Rezaei. "Performance Analysis of Reversible Sequential Circuits Based on Carbon NanoTube Field Effect Transistors (CNTFETs)". فناوری آموزش, 6, 2, 1397, 173-183. doi: 10.22061/jecei.2019.5015.183
Shaveisi, M., Rezaei, A.. (1397). 'Performance Analysis of Reversible Sequential Circuits Based on Carbon NanoTube Field Effect Transistors (CNTFETs)', فناوری آموزش, 6(2), pp. 173-183. doi: 10.22061/jecei.2019.5015.183
Shaveisi, M., Rezaei, A.. Performance Analysis of Reversible Sequential Circuits Based on Carbon NanoTube Field Effect Transistors (CNTFETs). فناوری آموزش, 1397; 6(2): 173-183. doi: 10.22061/jecei.2019.5015.183

Performance Analysis of Reversible Sequential Circuits Based on Carbon NanoTube Field Effect Transistors (CNTFETs)

Journal of Electrical and Computer Engineering Innovations (JECEI)
مقاله 6، دوره 6، شماره 2، مهر 2018، صفحه 173-183    اصل مقاله (1.59 M)
نوع مقاله: Original Research Paper
شناسه دیجیتال (DOI): 10.22061/jecei.2019.5015.183
نویسندگان
M. Shaveisi* ؛ A. Rezaei
Department of Electrical Engineering, Kermanshah University of Technology, Kermanshah, Iran
تاریخ دریافت: 31 مرداد 1396،  تاریخ بازنگری: 09 اسفند 1396،  تاریخ پذیرش: 09 خرداد 1397 
چکیده
Background and Objectives: This study presents the importance of reversible logic in designing of high performance and low power consumption digital circuits. In our research, the various forms of sequential reversible circuits such as D, T, SR and JK flip-flops are investigated based on carbon nanotube field-effect transistors.
Methods: By simultaneous using of the reversible logic gates and carbon nanotube transistors in implementation of various flip-flops and introducing suitable transistor circuits of conventional reversible gates, all reversible flip-flops are simulated in two voltages, 0.3 and 0.5 Volt. The Hspice_H-2013.03-SP2 software is used to simulate these circuits using the 32nm CNTFET technology (the standard Stanford spice model).
Results: The simulation results indicate a significant reduction in the average power consumption of D, T, SR and JK flip-flops, respectively about 99.98%, 82.79%, 60.46%, and 81.53%.
Conclusion: Our results show that the proposed structures have achieved a high performance in terms of average power consumption and PDP.


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Copyrights
©2018 The author(s). This is an open access article distributed under the terms of the Creative Commons Attribution (CC BY 4.0), which permits unrestricted use, distribution, and reproduction in any medium, as long as the original authors and source are cited. No permission is required from the authors or the publishers.
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کلیدواژه‌ها
Reversible logic؛ Sequential circuit؛ Carbon nanotube field effect transistor؛ Flip-flop؛ Power consumption
مراجع
[1]R. Landauer, “Irreversibility and heat generation in the computing process,” IBM Journal of Research and Development, 5(3): 183-191, 1961.

[2]C. H. Bennett, “Logical reversibility of computation,” IBM Journal of Research and Development, 17(6): 525-532, 1973.

[3] R. Singh,  M. K. Pandey, “Design and optimization of sequential counters using a novel reversible gate,” presented at the 2016 International Conference on Computing, Communication and Automation (ICCCA), Noida, India, 2016.

[4] H. Rohini, S. Rajashekar, P. Kumar, “Design of basic sequential circuits using reversible logic,” presented at the 2016 International Conference on Electrical, Electronics, and Optimization Techniques (ICEEOT), Chennai, India, 2016.

[5] P. Joshi, I. Sahu, “A review paper on design of an asynchronous counter using novel reversible SG gate,” presented at the 2017 International Conference on Innovative Mechanisms for Industry Applications (ICIMIA), Bangalore, India, 2017.

[6] M. A. L. Abir et al., “Design of parity preserving reversible sequential circuits,” presented at the 2016 5th International Conference on Informatics, Electronics and Vision (ICIEV), Dhaka, Bangladesh, 2017.

[7] M. H. Khan, J. E. Rice, “Improved synthesis of reversible sequential circuits,” presented at the 2016 IEEE International Symposium on Circuits and Systems (ISCAS), Montreal, Canada, 2016.

[8] P. Singh, R. Chandel, “Design and performance analysis of digital circuits using carbon nanotube transistors,” presented at the 2017 International Conference on Inventive Communication and Computational Technologies (ICICCT), Coimbatore, India, 2017.

[9] M. Kartalaeih, H. Sharifi, “Analysis and simulation of carbon nanotubes structure and application CNT on the based circuits and their introduction to a new low power delay flip flop,” Journal of Scientific Research and Development, 2(4): 277-285, 2015.

[10] S. L. Murotiya, A. Gupta., “Design and analysis of CNTFET based D-Flip-Flop,” International Journal of Electronics and Communication Engineering & Technology (IJECET), 4(7): 144-149, 2013.

 [11] A. Sahai, V. Sharma, “Design of low power CNTFET based D flip flop using sleep transistor technique,” International Journal of Engineering Research & Technology (IJERT), 4(4): 541-545, 2015.

[12] M. Dadashi Gavaber, K. Manochehri Kalantari, , S. Pourmozafari, “Design of high speed and low power D Flip-Flop by CNTFET technology,” presented at the 3rd International Conference on Knowledge-Based Engineering and Innovation, Tehran, Iran, 2016.

[13] N. Talebipoor, p. Keshavarzian, B. Irannejad, “Low power and high speed D-latch circuit designs based on carbon nanotube FET,” International Journal of Engineering and Technology, 2(1): 12-16, 2013.

[14] S. Lin, Y. B. Kim, F. Lombardi, "Design of a CNTFET-based SRAM cell by dual-chirality selection,” IEEE Transactions on Nanotechnology, 9(1): 30-37, 2010.

[15] M. Bagherizadeh and M. Eshghi, ‘Two novel low-power and high-speed dynamic carbon nanotube full-adder cells,” Nanoscale Research Letters, 6(1): 519, 2011.

[16] A. V. Lakshmi, S. Sagadevan, “Low power implementation of sequential circuits using reversible logic gates,” International Journal of Current Engineering and Technology, 4(3): 2108-2111, 2014.

[17] M. S. Al Mamun, D. Menville, “Quantum cost optimization for reversible sequential circuit,” International Journal of Advanced Computer Science and Applications, 4(12): 15-21, 2013.

[18] M. Mohammadi, M. Eshghi, “Behavioral description of quantum V and V+ gates to design quantum logic circuits,” presented at the 2008 5th International Multi-Conference on Systems, Signals and Devices, Amman, Jordan, 2008.

[19] K. P. Raj, Y. Syamala, “Transistor level implementation of digital reversible circuits,” International Journal of VLSI Design & Communication Systems, 5(6): 43-61, 2014.

[20] G. C. Naguboina, K. Anusudha, “Design and synthesis of combinational circuits using reversible decoder in Xilinx,” presented at the 2017 International Conference on Computer, Communication and Signal Processing (ICCCSP), Chennai, India, 2017.

[21] M. Hossain, et al., “A new design technique of reversible BCD adder based on NMOS with pass transistor gates,” International Journal of VLSI design & Communication Systems (VLSICS), 2(4): 15-26, 2011.  

[22] N. Srinivasan, et al., “Power reduction by clock gating technique,” Procedia Technology, 21: 631-635, 2015.   

[23] H. Thapliyal, N. Ranganathan, S. Kotiyal, “Design of testable reversible sequential circuits,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 21(7): 1201-1209, 2013. 

[24] S. Ziabakhsh and M. Zoghi, “Design of a low-power high-speed t-flip-flop using the gate-diffusion input technique,” in Proc. 17th Telecommunications forum TELFOR: 1470-1473, 2009. Available:

[25] H. Thapliyal, N. Ranganathan, “Design of reversible sequential circuits optimizing quantum cost, delay, and garbage outputs,” ACM Journal on Emerging Technologies in Computing Systems (JETC), 6(4): 14:1-14:31, 2010.

[26] P. R. Yelekar, S. S. Chiwande, “Design of sequential circuit using reversible logic,” presented at the IEEE-International Conference on Advances in Engineering, Science and Management (ICAESM -2012), Tamil Nadu, India, 2012.  

[27] K. Dhar, “Design of a high speed, low power synchronously clocked NOR-based JK flip-flop using modified GDI technique in 45nm technology,” presented at the 2014 International Conference on Advances in Computing, Communications and Informatics (ICACCI), New Delhi, India, 2014.  

[28] A. Sengupta, P. Pande, “Comparative study of the methodologies used in low-power master–slave flip-flops,” in Proc. of International Conference on Intelligent Communication, Control and Devices, 479: 127-133, 2017.

[29] V. A. Lakshman, R. Sakthivel, “Design of high performance power efficient flip flops using transmission gates,” presented at the 2016 International Conference on Circuit, Power and Computing Technologies (ICCPCT), Nagercoil, India, 2016.

[30] A. Karimi, A. Rezai, M. M. Hajhashemkhani, “A novel design for ultra-low power pulse-triggered D-Flip-Flop with optimized leakage power,” Integration, the VLSI Journal, 60: 160-166, 2018.

[31] P. Meher, K. K. Mahapatra, “A low-power CMOS flip-flop for high performance processors,” presented at the TENCON 2014-2014 IEEE Region 10 Conference, Bangkok, Thailand, 2014.

[32] E. Abiri, M. R. Salehi, A. Darabi, “Design and simulation of low-power and high speed T-Flip Flap with the modified gate diffusion input (GDI) technique in nano process,” presented at the 2014 22nd Iranian Conference on Electrical Engineering (ICEE), Tehran, Iran, 2014.

[33] V. Savani, N. Devashrayee, “Analysis & characterization of dual tail current based dynamic latch comparator with modified SR latch using 90nm technology,” presented at the 2015 19th International Symposium on VLSI Design and Test, Ahmedabad, India, 2015.

[34] S. E. Thomas, “Design of flip-flops for high performance VLSI applications using different CMOS technologies,” International Journal of Advance Research, Ideas and Innovations in Technology, 4(1): 193-198, 2018.

 

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