تعداد نشریات | 11 |
تعداد شمارهها | 208 |
تعداد مقالات | 2,090 |
تعداد مشاهده مقاله | 2,829,637 |
تعداد دریافت فایل اصل مقاله | 2,049,134 |
A-New-Closed-form-Mathematical-Approach-to-Achieve Minimum Phase Noise in Frequency Synthesizers | ||
Journal of Electrical and Computer Engineering Innovations (JECEI) | ||
مقاله 2، دوره 2، شماره 1 - شماره پیاپی 3، فروردین 2014، صفحه 7-13 اصل مقاله (406.89 K) | ||
نوع مقاله: Original Research Paper | ||
شناسه دیجیتال (DOI): 10.22061/jecei.2014.37 | ||
نویسندگان | ||
S. SamadiGorji؛ B. Zakeri* ؛ M.R. Zahabi | ||
Babol Nushirvani University of Technology, Department of Electrical Engineering, Babol, Iran | ||
تاریخ دریافت: 28 مهر 1392، تاریخ بازنگری: 24 آذر 1392، تاریخ پذیرش: 24 آذر 1392 | ||
چکیده | ||
The aim of this paper is to minimize output phase noise for the pure signal synthesis in the frequency synthesizers. For this purpose, first, an exact mathematical model of phase locked loop (PLL) based frequency synthesizer is described and analyzed. Then, an exact closed-form formula in terms of synthesizer bandwidth and total output phase noise is extracted. Based on this formula, the phase noise diagram as a function of bandwidth is plotted. From the analysis and simulation results, it is observed that the synthesizer has a minimum phase noise at a particular bandwidth. | ||
کلیدواژهها | ||
Frequency synthesizers؛ Phase noise؛ Phase-locked loop؛ Phase noise reduction | ||
مراجع | ||
[1] B. Razavi, “RF Microelectronics,” 2nd ed, Prentice-Hall, 2011, p. 638.
[2] P. EnSu, S. Pamarti, “Fractional‐N Phase‐Locked‐Loop‐Based Frequency Synthesis: A Tutorial,” IEEE Trans. Circuits and Systems—II: Express Briefs, Vol. 56, No. 12, pp. 881—885, December 2009.
[3] Y. W. Kim, and J. D. Yu, “Phase Noise Model of Single Loop Frequency Synthesizer,” IEEE Trans. on Broadcasting, vol. 54, NO. 1, pp. 112‐119, March. 2008.
[4] X. Yan, X. Kuang, and N. Wu, “An Accurate and Fast Behavioral Model for PLL Frequency Synthesizer Phase Noise/Spurs Prediction,” IEEE Custom Integrated Circuits Conference, pp. M‐ 17‐1—M‐17‐4, Sept. 2009.
[5] A. Hajimiri, “Noise in Phase‐Locked Loops,” Symp. on MixedSignal Design, pp. 1‐6, Feb. 2001.
[6] F. M. Gardner, “Charge‐Pump Phase‐Locked Loops,”IEEE Trans. Comm., Vol. COM‐28, pp.1849‐1858, November 1980. [7] P. K. Hanumolu, M. Brownlee, K. Mayaram, and U. K. Moon, “Analysis of Charge‐Pump Phase‐Locked Loops,” IEEE Trans. on Circuit and Systems–I, Vol. 51, No. 9, pp. 1665–1674, September 2004.
[8] A. Lacaita, S. Levantino, and C. Samori, “Integrated Frequency Synthesizers for Wireless Systems,” UK: Cambridge, 2007.
[9] A. Holme, “15‐25MHz Fractional‐N Synthesizer,” 2005. [Online]. Available at: http://www.holmea.demon.co.uk/Frac2/Mash.htm.
[10] M.H. Perrott, M.D. Trott, and C.G. Sodini, “A Modeling Approach for Sigma‐Delta Fractional‐N Frequency Synthesizers Allowing Straightforward Noise Analysis,” IEEE J. Solid‐State Circuits, Vol. 37, No. 8, pp. 1028‐‐1038, 2002.
[11] H. C. Luong, G. C. Leung, “LowVoltage CMOS RF Frequency Synthesizers,” Cambridge University Press, 2004. [12] Dean Banerjee, “PLLPerformance, Simulation and Design Handbook,,”(4thEdition), 2008, [online]. Available at:http://ww w.national.com/appinfo/wireless/pll_design book.
[13] A. Hajimiri, T. H. Lee, “A General Theory of Phase Noise in Electrical Oscillators,”IEEE J. SolidState Circuits, Vol. 33, No. 2, pp. 179‐194, Feb. 1998.
[14] D. Ham and A. Hajimiri, “Concepts and Methods in Optimization of Integrated LC VCOs,” IEEE J. SolidState Circuits, Vol. 36, No. 6, June 2001.
[15] J. Craninckx and M. Steyaert, “Low‐noise voltage controlled oscillators using enhanced LC‐tanks,” IEEE Trans. Circ.Syst.II, Vol. 42, pp. 794‐904, Dec. 1995.
[16] S. Norsworthy, R. Schreier, and G. Temes, “Delta‐Sigma DataConverters: Theory, Design, and Simulation,” IEEE Press, 1997.
[17] W. Gao, X. Gao, “Design of PLL frequency synthesizer based on the fourth‐order active filter,” IEEE Conf., ISSSE, International Symposium, Vol. 2, pp. 1‐3, Sept. 2010 | ||
آمار تعداد مشاهده مقاله: 3,715 تعداد دریافت فایل اصل مقاله: 1,655 |