دانشگاه تربیت دبیر شهید رجائی
انتشارات دانشگاه تربیت دبیر شهید رجائی

  اخبار و اعلانات

 آمار

تعداد نشریات11
تعداد شماره‌ها207
تعداد مقالات2,061
تعداد مشاهده مقاله2,769,944
تعداد دریافت فایل اصل مقاله2,003,296
Asadi Ghiasvand, G., Zare, M., Mahdavi, M.. (1402). A New High-Speed Multi-Layer Three-Bits Counter Design in Quantum-Dot Cellular Automata Technology. فناوری آموزش, 12(1), 235-246. doi: 10.22061/jecei.2023.9955.667
G. Asadi Ghiasvand; M. Zare; M. Mahdavi. "A New High-Speed Multi-Layer Three-Bits Counter Design in Quantum-Dot Cellular Automata Technology". فناوری آموزش, 12, 1, 1402, 235-246. doi: 10.22061/jecei.2023.9955.667
Asadi Ghiasvand, G., Zare, M., Mahdavi, M.. (1402). 'A New High-Speed Multi-Layer Three-Bits Counter Design in Quantum-Dot Cellular Automata Technology', فناوری آموزش, 12(1), pp. 235-246. doi: 10.22061/jecei.2023.9955.667
Asadi Ghiasvand, G., Zare, M., Mahdavi, M.. A New High-Speed Multi-Layer Three-Bits Counter Design in Quantum-Dot Cellular Automata Technology. فناوری آموزش, 1402; 12(1): 235-246. doi: 10.22061/jecei.2023.9955.667

A New High-Speed Multi-Layer Three-Bits Counter Design in Quantum-Dot Cellular Automata Technology

Journal of Electrical and Computer Engineering Innovations (JECEI)
مقاله 16، دوره 12، شماره 1، فروردین 2024، صفحه 235-246    اصل مقاله (1.47 M)
نوع مقاله: Original Research Paper
شناسه دیجیتال (DOI): 10.22061/jecei.2023.9955.667
نویسندگان
G. Asadi Ghiasvand1؛ M. Zare* 1؛ M. Mahdavi2
1Department of Electronic Engineering, Shahr-e-Qods Branch, Islamic Azad University, Tehran, Iran.
2Department of Electronic Engineering, Shahr-e-Qods Branch, Islamic Azad University, Tehran, Iran.
تاریخ دریافت: 02 مرداد 1402،  تاریخ بازنگری: 07 آبان 1402،  تاریخ پذیرش: 14 آبان 1402 
چکیده
Background and Objectives: Quantum-dot Cellular Automata technology is a new method for digital circuits and systems designs. This method can be attractive for researchers due to its special features such as power consumption, high calculation speed and small dimensions.
Methods: This paper tries to design a three-bits counter with minimum area and delay among the other circuits. As the circuit dimensions are reduced, the area and consequently, the delay are decreased, too. Therefore, this paper tries to design a three-bits counter with minimum dimensions and delay. The proposed counter contains 96 cells and is designed in three layers. It has the least area and delay compared to the priors.
Results: The circuit simulation illustrates 0.08 µm2 of area occupation and one clock cycle delay. In comparison with the best previous design, which includes 110 cells, the cells number, area and delay are decreased by 12.72%, 27.27% and 33.33%, respectively. Also, the cost of the circuit has been improved by 54.32%. The power analysis of the design shows 13% reduction in the total energy dissipation of the circuit compared to the best prior work. The circuit reliability versus temperature variations has been simulated and the results represent suitable stability. The fault tolerance of the circuit which is occurred by the displacement faults represents normal operation of the circuit.
Conclusion: As the counter is an element which is implemented in several digital systems, its area reduction causes the whole system area to be reduced. Also, the circuit delay has been decreased significantly which means that the circuit can be employed by high speed systems.
کلیدواژه‌ها
Digital circuit design؛ Quantum-Dot-Cellular Automata؛ Multi-layers design؛ Three Bits Counter
مراجع
[1] K. Jeong, A. B. Kahng, “A power-constrained MPU roadmap for the International Technology Roadmap for Semiconductors (ITRS),” in Proc. 2009 international SoC Design Conference (ISOCC), 2009.

[2] R. Chakrabarty, D. Kumar Mahato, A. Banerjee, S. Choudhuri, M. Dey, N. K. Mandal, "A novel design of flip-flop circuits using quantum dot cellular automata (QCA)," in Proc. 2018 IEEE 8th Annual Computing and Communication Workshop and Conference (CCWC): 408-414, 2018.

[3] H. Cho, E. E. Swartzlander, “Adder and multiplier design in quantum-dot cellular automata,” IEEE Trans. Comput., 58(6): 721-727, 2009.

[4] M. A. Dehkordi, A. S. Shamsabadi, B. S. Ghahfarokhi, A. Vafaei, “Novel RAM cell designs based on inherent capabilities of quantum-dot cellular automata,” Microelectron. J., 42(5): 701-708, 2011.

[5] M. N. Asfestani, S. R. Heikalabad, “A novel multiplexer-based structure for random access memory cell in quantum-dot cellular automata,” Phys. B: Condens. Matter, 521: 162-167, 2017.

[6] C. S. Lent, P. D. Tougaw, W. Porod, G. H. Bernstein, “Quantum cellular automata,” Nanotechnology, 4(1): 49-57, 1993.

[7] S. Angizi, S. Sayedsalehi, A. Roohi, N. Bagherzadeh, K. Navi, "Design and verification of new n-bit quantum-dot synchronous counters using majority function-based JK flip-flops," J. Circuits Syst. Comput., 24(10): 1550153, 2015.

[8] K. S. Bhavani, V. Alinvinisha, "Utilization of QCA based T flip flop to design Counters," in Proc. 2015 International Conference on Innovations in Information, Embedded and Communication Systems (ICIIECS): 1-6, 2015.

[9] S. Angizi, M. H. Moaiyeri, S. Farrokhi, K. Navi, N. Bagherzadeh, "Designing quantum-dot cellular automata counters with energy consumption analysis," Microprocess. Microsyst., 39(7): 512-520, 2015.

[10] M. Abutaleb, “Robust and efficient quantum-dot cellular automata synchronous counters,” Microelectron. J., 61: 6-14, March. 2017.

[11] Z. Amirzadeh, M. Gholami, “Counters designs with minimum number of cells and area in the quantum-dot cellular automata technology,” Int. J. Theor. Phys., 58: 1758-1775, 2019.

[12] A. H. Majeed, E. Alkaldy, M. S. bin Zainal, D. Bin MD Nor, “Synchronous counter design using novel level sensitive T-FF in QCA technology,” J. Low Power Electron. Appl., 9(3): 27, 2019.

[13] J. Mohammadi, M. Zare, M. Molaei, M. Maadani, "Low-cost three-bit counter design in quantum-dot cellular automata technology," IETE J. Res., 2022.

[14] C. S. Lent, P. D. Tougaw, “Lines of interacting quantum‐dot cells: A binary wire,” J. Appl. Phys., 74(10): 6227-6233, 1993.

[15] F. Lombardi, J. Huang, "Design and test of digital circuits by quantum-dot cellular automata," Artech House, Inc., Electronic ISBN:9781596932685, 2007.

[16] P. D. Tougaw, C. S. Lent, "Logical devices implemented using quantum cellular automata," J. Appl. Phys., 75(3): 1818-1825, 1994.

[17] C. S. Lent, P. D. Tougaw, “A device architecture for computing with quantum dots,” Proc. IEEE, 85(4): 541-557, 1997.

[18] B. Sen, M. Dalui, B. K. Sikdar, “Introducing universal qca logic gate for synthesizing symmetric functions with minimum wire crossings,” in Proc. ICWET: 828–833, 2010.

[19] G. Schulhof, Konrad, G. A. Jullien, “Simulation of random cell displacements in qca,” J. Emerg. Technol. Comput. Syst., 3(1), 2007.

[20] K. Walus, G. Schulhof, G. A. Jullien, “High level exploration of Quantum-Dot Cellular Automata (QCA),” in Proc. 38th Asilomar Conference on Signals, Systems and Computers: 30–33, 2004.

[21] A. Gin, P. D. Tougaw, S. Williams, “An alternative geometry for quantum-dot cellular automata,” J. Appl. Phys., 85(12): 8281–8286, 1999.

[22] I. L. Bajec, P. Pecar, “Two-layer synchronized ternary quantum-dot cellular automata wire crossings,” Nanotechnol., 7: 368–376, 2012.

[23] B. Sen, A. Nag, A. De, B. K. Sikdar, “Multilayer Design of QCA Multiplexercellular,” in Proc. 2013 Annual IEEE India Conference (INDICON), 2013.

[24] W. Liu, L. Liang, M. O’Neill, E. Swartzlander, "A first step towards cost functions for quantum-dot cellular automata designs," IEEE Trans. Nanotechnol., 13(3): 476-487, 2014.

[25] S. S. Roy, "Fault tolerance and temperature stability: the dynamic error estimation in quantum-dot cellular automata," in proc. 2017 IEEE International Symposium on Nanoelectronic and Information Systems (iNIS): 84-89, 2017.

[26] D. Bhowmik, J. Pal, M. Chandra, A. K. Saha, N. Kumar, "QCA based design of cost-efficient code converter with temperature stability and energy efficiency analysis," Mater. Today Proc., 49(8): 3585-3594 , 2022.

[27] B. Sen, A. Nag, A. De, B. K. Sikdar, "Towards the hierarchical design of multilayer QCA logic circuit," J. Comput. Sci., 11: 233-244, 2005.

[28] J. Pal, S.  Bhattacharjee, A. K.  Saha, P.  Dutta , " Study on temperature stability and fault tolerance of adder in quantum-dot cellular automata," in Proc. 5th IEEE International Conference on Signal Processing, Computing and Control (ISPCC 2k19), 2019.

[29] M. Momenzadeh, H. Jing, M. B. Tahoori, F. Lombardi, "Characterization, test, and logic synthesis of and-or-inverter (AOI) gate design for QCA implementation," IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 24 (2005): 1881-1893, 2005.

[30] A. Roohi, R. F. DeMara, N. Khoshavi, "Design and evaluation of an ultra-area-efficient fault-tolerant QCA full adder," Microelectron. J., 46(6): 531-542, 2015.

 

آمار
تعداد مشاهده مقاله: 221
تعداد دریافت فایل اصل مقاله: 114


سامانه مدیریت نشریات علمی. قدرت گرفته از سیناوب