CNN-Based Placement and Multi-Objective Routing for Analog Circuits with Simulated Annealing and NSGA-III

Gholami Boorkheyli, Atousa; Babaeinik, Majid; Dehbovid, Hadi; Ghods, Vahid

doi:10.22061/jecei.2025.12133.866

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	CNN-Based Placement and Multi-Objective Routing for Analog Circuits with Simulated Annealing and NSGA-III
Journal of Electrical and Computer Engineering Innovations (JECEI)
مقاله 10، دوره 14، شماره 2، مهر 2026، صفحه 411-424 اصل مقاله (1.37 M)
نوع مقاله: Original Research Paper
شناسه دیجیتال (DOI): 10.22061/jecei.2025.12133.866
نویسندگان
Atousa Gholami Boorkheyli¹؛ Majid Babaeinik¹؛ Hadi Dehbovid^* ²؛ Vahid Ghods¹
¹Department of Electrical Engineering, Se.C., Islamic Azad University, Semnan, Iran.
²Department of Electrical Engineering, No.C., Islamic Azad University, Noor, Iran.
تاریخ دریافت: 29 تیر 1404، تاریخ بازنگری: 04 آبان 1404، تاریخ پذیرش: 12 آبان 1404
چکیده
Background and Objectives: This research aims to optimize component placement in integrated systems using evolutionary algorithms. The primary goal is to generate a compact floorplan while satisfying design constraints, particularly in analog circuits where symmetry and proximity constraints are critical to minimizing coupling interference and enhancing performance. The study proposes using a convolutional neural network (CNN) to extract these placement constraints, with its parameters optimized via the non-dominated sorting genetic algorithm III (NSGA-III). Additionally, a hybrid routing approach combining simulated annealing (SA) and NSGA-III is introduced to improve routing efficiency through multi-objective optimization. Methods: The placement constraints, including symmetry and proximity requirements, are extracted using a CNN, whose parameters are optimized by NSGA-III. For routing, a hybrid approach is employed where SA generates initial routing solutions, which are then refined by NSGA-III for multi-objective optimization. The proposed method is implemented on a two-stage recycling folded cascade (RFC) amplifier in 0.18μm CMOS technology with a 1.8V supply voltage. A dedicated MATLAB toolbox is developed to facilitate placement while adhering to design rules using optimization algorithms. Results: Simulation results confirm the effectiveness of the proposed methodology, demonstrating optimized placement and routing with improved circuit performance. The combination of CNN and NSGA-III successfully generates a compact and efficient layout, while the hybrid routing approach (SA + NSGA-III) enhances the routing process. The RFC amplifier case study shows better utilization of physical resources and performance improvements, validating the method's efficiency. Conclusion: This study demonstrates that the proposed method, integrating evolutionary algorithms and CNN, effectively optimizes placement and routing in integrated systems. The CNN-based constraint extraction and NSGA-III optimization enable compact layouts, while the hybrid routing approach improves multi-objective optimization. Simulations on the RFC amplifier confirm enhanced circuit performance and resource utilization. This method offers significant advantages over traditional approaches and is applicable to complex and industrial designs.
کلیدواژه‌ها
Analog Circuit Placement؛ Evolutionary Algorithms؛ Convolutional Neural Network؛ NSGA-III, Simulated Annealing

مراجع
[1] G. G. E. Gielen, “CAD tools for embedded analogue circuits in mixed-signal integrated systems on chip,” IEE Proc. Comput. Digital Tech., 152(3): 317–332, 2005. [2] ITRS, (2010, Dec.), International Technology Roadmap for Semiconductors—Update. [3] G. G. E. Gielen, R. A. Rutenbar, “Computer-aided design of analog and mixed-signal integrated circuits,” in Proc. IEEE, 88(12): 1825–1852, 2000. [4] R. A. Rutenbar, “Analog layout synthesis: what’s missing?,” in Proc. the 19th international symposium on Physical design: 43, 2010. [5] E. S. Ochotta, T. Mukherjee, R. A. Rutenbar, L. R. Carley, Practical Synthesis of High-Performance Analog Circuits, Springer Publishing Company, 2012. [6] B. Razavi, Design of Analog CMOS Integrated Circuits, McGraw-Hill Education, Aug 15, 2000. [7] D. A. Johns, K. Martin, Analog Integrated Circuit Design, John Wiley & Sons, Aug 1, 2008. [8] A. S. Sedra, K. C. Smith, Microelectronic Circuits, Oxford University Press, 1998. [9] F. Maloberti, Analog Design for CMOS VLSI Systems, Kluwer Academic Publishers, 2003. [10] H. E. Graeb, Analog Layout Synthesis, Springer, New York, NY, USA, 2011. [11] J. M. Cohn, D. J. Garrod, R. A. Rutenbar, L. R. Carley, “KOAN/ANAGRAM II: new tools for device-level analog placement and routing,” IEEE J. Solid-State Circuits, 26(3): 330–342, Mar. 1991. [12] E. Malavasi, E. Charbon, E. Felt, A. Sangiovanni-Vincentelli, “Automation of IC layout with analog constraints,” IEEE Trans. Comput. Aided Design, 15(8): 923–942, 1996. [13] K. Lampaert, G. Gielen, W. Sansen, “A performance-driven placement tool for analog integrated circuits,” IEEE J. Solid-State Circuits, 30(7): 773–780, 1995. [14] P. Y. Chou, H. C. Ou, Y. W. Chang, “Heterogeneous B∗-trees for analog placement with symmetry and regularity considerations,” in Proc. 2011 IEEE/ACM International Conference on Computer-Aided Design (ICCAD): 512 – 516, 2011. [15] H. C. C. Chien, H. C. OU, T. C. Chen, T. Y. Kuan, Y. W. Chang, “Double patterning lithography-aware analog placement,” in Proc. the 50^th Annual Design Automation Conference, 4: 1-6, 2013. [16] X. Chen, J. Hu, N. Xu, “Regularity-constrained floorplanning for multi-core processors,” Integration the VLSI J., 47(1): 86–95, 2014. [17] F. Balasa, S. C. Maruvada, K. Krishnamoorthy, “Efficient solution space exploration based on segment trees in analog placement with symmetry constraints,” in Proc. IEEE/ACM International Conference on Computer-Aided Design: 497–502, 2002. [18] F. Balasa, S. C. Maruvada, K. Krishnamoorthy, “On the exploration of the solution space in analog placement with symmetry constraints,” IEEE Trans. Comput. Aided Design, 23(2): 177–191, 2004. [19] D. Long, X. Hong, S. Dong, “Signal-path driven partition and placement for analog circuit,” in Proc. the 2006 Asia and South Pacific Design Automation Confere: 694–699, 2006. [20] L. Zhang, Y. Jiang, “Global-routing driven placement strategy in analog VLSI physical designs,” in Proc. 48th Midwest Symposium on Circuits and Systems: 1239 - 1242, 2005. [21] H. C. Ou, H. C. Chang Chien, Y. W. Chang, “Simultaneous Analog Placement and Routing with Current Flow and Current Density Considerations,” in Proc. 50th ACM/EDAC/IEEE Design Automation Conference (DAC): 1-6, 2013. [22] J. Togni, F. R. Schneider, V. P. Correia, R. P. Ribas, A. I. Reis, “Automatic generation of digital cell libraries,” in IEEE Proc. 15th Symposium on Integrated Circuits and Systems Design: 265-270, 2002. [23] M. M. Ozdal, R. F. Hentschke, “Maze routing algorithms with exact matching constraints for analog and mixed signal designs,” in Proc. IEEE/ACM International Conference on Computer-Aided Design (ICCAD): 130 – 136, 2012. [24] P. K. Rout, D. P. Acharya, “Digital circuit placement in FPGA based on efficient particle swarm optimization techniques,” in Proc. International Conference on Industrial and Information Systems (ICIIS): 224 – 227, 2010. [25] D. Li, L. Wang, Y. Shen, S. Liu, Z. Zhu, “A background timing skew calibration for time-interleaved ADCs based on frequency fitness genetic algorithm,” IEEE Trans. Instrum. Meas., 73: 1–10, 2024. [26] M. Campilho-Gomes, R. Tavares, J. Goes, “Analog flat-level circuit synthesis with genetic algorithms,” IEEE Access, 12: 115532–115545, 2024. [27] K. Deb, H. Jain, “An evolutionary many-objective optimization algorithm using reference-point-based nondominated sorting approach, part I: solving problems with box constraints,” IEEE Trans. Evol. Comput., 18, (4): 577-601, 2014. [28] A. Agarwal, J. Lang, Circuits, Electronics, MIT OpenCourseWare, Massachusetts Institute of Technology, 2007. [29] S. M. Anisheh, H. Abbasizadeh, H. Shamsi, C. Dadkhah, K. Y. Lee, “98-dB gain class-AB OTA with 100 pF load capacitor in 180-nm digital CMOS process,” IEEE Access, 7: 17772–17779, 2019. [30] B. Babazadeh Daryan, H. Khalesi, V. Ghods, “Four‐stage CMOS amplifier: Frequency compensated using differential block,” IET Circuits Devices Syst., 14(6): 762–769, 2020. [31] B. Babazadeh Daryan, H. Khalesi, V. Ghods, A. Izadbakhsh, “Multi-stage CMOS amplifier frequency compensation using a single MOSCAP,” Analog Integr. Circuits Signal Process., 103: 237–246, 2020. [32] S. M. Anisheh, H. Shamsi, “Placement and routing method for analogue layout generation using modified cuckoo optimisation algorithm,” IET Circuits Devices Syst., 12(5): 532–541, 2018. [33] K. Bandla, D. Pal, “Strong-ARM dynamic latch comparators: design and analyses on CAD platform,” arXiv:2402.14519, 2024.
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CNN-Based Placement and Multi-Objective Routing for Analog Circuits with Simulated Annealing and NSGA-III