Faculty of Electrical Engineering - Sari Branch, Islamic Azad University, Sari, Iran.
تاریخ دریافت: 24 دی 1403،
تاریخ بازنگری: 23 فروردین 1404،
تاریخ پذیرش: 29 فروردین 1404
چکیده
Background and Objectives: A Time-to-Digital Converter (TDC) is a fundamental electronic component that converts time intervals into digital representations. It plays a critical role in high-precision applications such as particle physics experiments, time-of-flight measurements, and the processing of high-frequency signals in communication systems. This paper presents a comprehensive study on the design and simulation of two innovative low-power TDC architectures. Methods: The approach introduces a novel low-power D Flip-Flop (D-FF) circuit using transmission gates (TG) and CMOS inverters to reduce power consumption while maintaining high performance. Specialized low-power delay cells are proposed for Flash TDC implementation. Detailed simulations were conducted using Cadence software with a 0.18 μm CMOS fabrication process at a supply voltage of 1.8 V. Results: The results demonstrate significant improvements in power efficiency and performance metrics, indicating the potential of the proposed TDC designs for future applications requiring precise temporal measurements. The Figure of Merit (FOM) values of the two proposed structures are 0.033 and 0.020, respectively. Conclusion: Power consumption in TDCs is a critical factor, as it directly influences the overall efficiency of electronic systems. Reducing power consumption can lead to decreased energy use, improved thermal management, and an extended lifespan for devices. Conversely, higher power consumption can generate excessive heat, which can negatively impact the system's performance and reliability. Thus, it is vital to strike an optimal balance between accuracy and power consumption in TDCs to enhance the longevity of electronic devices. This paper presents the design of delay cell circuits and a D-FF using a 0.18 µm CMOS process with a 1.8 V supply voltage. The power consumption of the proposed delay cells has been minimized through the application of the body bias technique. The performance of the delay cell has been evaluated in flash TDC circuits, and the results demonstrate the effective performance of the proposed structures.
