An Adaptive Routing Algorithm for Wireless Network on Chips

Tajary, A.; Tahanian, E.

doi:10.22061/jecei.2022.8464.518

تعداد نشریات	13
تعداد شماره‌ها	238
تعداد مقالات	2,418
تعداد مشاهده مقاله	3,962,362
تعداد دریافت فایل اصل مقاله	2,874,084

	An Adaptive Routing Algorithm for Wireless Network on Chips
Journal of Electrical and Computer Engineering Innovations (JECEI)
مقاله 20، دوره 10، شماره 2، مهر 2022، صفحه 487-496 اصل مقاله (960.78 K)
نوع مقاله: Original Research Paper
شناسه دیجیتال (DOI): 10.22061/jecei.2022.8464.518
نویسندگان
A. Tajary^* ؛ E. Tahanian
Faculty of Computer Engineering, Shahrood University of Technology, Shahrood, Iran.
تاریخ دریافت: 25 آذر 1400، تاریخ بازنگری: 27 بهمن 1400، تاریخ پذیرش: 31 فروردین 1401
چکیده
Background and Objectives: Wireless Network on Chip (WNoC) is one of the promising interconnection architectures for future many-core processors. Besides the architectures and topologies of these WNoCs, designing an efficient routing algorithm that uses the provided frequency band to achieve better network latency is one of the challenges. Methods: Using wireless connections reduces the number of hops for sending data in a network, which can lead to lower latency for data delivery and higher throughput in WNoCs. On the other hand, since using wireless links reduces the number of hops for data transfer; this can result in congestion around the wireless nodes. The congestion may result in more delay in data transfer which reduces the network throughput of WNoCs. Although there are some good routing algorithms that balance traffic using wired and wireless connections for synthetic traffic patterns, they cannot deal with dynamic traffic patterns that existed in real-world applications. In this paper, we propose a new routing algorithm that uses the wireless connections as much as possible, and in the case of congestion, it uses the wired connection instead. Results: We investigated the proposed method using eight applications from the Parsec benchmark suite. Simulation results show that the proposed method can achieve up to 13.9% higher network throughput with a power consumption reduction up to 1.4%. Conclusion: In this paper, we proposed an adaptive routing algorithm that uses wireless links to deliver data over the network on chip. We investigated the proposed method on real-work applications. Simulation results show that the proposed method can achieve higher network throughput and lower power consumption.
کلیدواژه‌ها
Wireless Network on Chip؛ Routing؛ NoC

مراجع
[1] H. Jang et al., “Developing a multicore platform utilizing open risc-v cores,” IEEE Access, 9: 120010–120023, 2021. [2] P. Kansakar, A. Munir, “A design space exploration methodology for parameter optimization in multicore processors,” IEEE Trans. Parallel Distrib. Syst., 29(1): 2–15, 2018. [3] Y. Liu, S. Kato, M. Edahiro, “Analysis of memory system of tiled many-core processors,” IEEE Access, 7: 18964–18977, 2019. [4] A. Vijaya Bhaskar, T. Venkatesh, “Performance analysis of network-on-chip in many-core processors,” J. Parallel Distrib. Comput., 147: 196–208, 2021. [5] F.N. Sibai, “A two-dimensional low-diameter scalable on-chip network for interconnecting thousands of cores,” IEEE Trans. Parallel Distrib. Syst., 23(2): 193–201, 2012. [6] A. Balakrishnan, A. Naeemi, “Optimal global interconnects for networks-on-chip in many-core architectures,” IEEE Electron Device Lett., 31(4): 290–292, 2010. [7] S.D. Chawade, M.A. Gaikwad, R.M. Patrikar, “Review of xy routing algorithm for network-on-chip architecture,” Int. J. Comput. Appl., 43(21): 975–8887, 2012. [8] B. Bahrami, M.A. Jabraeil Jamali, S. Saeidi, “A novel hierarchical architecture for wireless network-on-chip,” J. Parallel Distrib. Comput., 120: 307–321, 2018. [9] E. Tahanian, A. Tajary, M. Rezvani, M. Fateh, “Scalable thz network-on-chip architecture for multichip systems,” J. Comput. Netw. Commun., 2020: 8823938, Dec. 2020. [10] B. Halavar, B. Talawar, “Power and performance analysis of 3D network-on-chip architectures,” Comput. Electr. Eng., 83: 106592, 2020 [11] Z. Wang, H. Gu, Y. Chen, Y. Yang, K. Wang, “3D network-on-chip design for embedded ubiquitous computing systems,” J. Syst. Archit., 76: 39–46, 2017. [12] Z. Liu, G. Song, Y. Zhou, Z. Zhang, F. Cheng, “Layout exploration for three-dimensional networks-on-chip: Chemical equilibrium simulation approach,” Microelectron. J., 115: 105195, 2021. [13] D.A. Hamdi, S. Ghoniemy, Y. Dakroury, M.A. Sobh, “A scalable software defined network orchestrator for photonic network on chips,” IEEE Access, 9: 35371–35381, 2021. [14] K. Sharma, V.K. Sehgal, “Energy-efficient and sustainable communication in optical networks on chip,” Sustainable Comput: Inform. Syst., 28: 100426, 2020. [15] A.B. Ahmed, T. Yoshinaga, A.B. Abdallah, “Scalable photonic networks-on-chip architecture based on a novel wavelength-shifting mechanism,” IEEE Trans. Emerg. Top. Comput., 8(2): 533–544, 2020. [16] D. DiTomaso, A. Kodi, D. Matolak, S. Kaya, S. Laha, W. Rayess, “A-winoc: Adaptive wireless network-on-chip architecture for chip multiprocessors,” IEEE Trans. Parallel Distrib. Syst., 26(12): 3289–3302, 2015. [17] H.K. Mondal, S.H. Gade, M.S. Shamim, S. Deb, A. Ganguly, “Interference-aware wireless network-on-chip architecture using directional antennas,” IEEE Trans. Multi-Scale Comput. Syst., 3(3): 193–205, 2017. [18] N. Mansoor, P.J.S. Iruthayaraj, A. Ganguly, “Design methodology for a robust and energy-efficient millimeter-wave wireless network-on-chip,” IEEE Trans. Multi-Scale Comput. Syst., 1(1): 33–45, 2015. [19] S. Abadal, J. Torrellas, E. Alarcón, A. Cabellos-Aparicio, “OrthoNoC: A broadcast-oriented dual-plane wireless network-on-chip architecture,” IEEE Trans. Parallel Distrib. Syst., 29(3): 628–641, 2018. [20] R.S. Narde, J. Venkataraman, A. Ganguly, I. Puchades, “Intra- and inter-chip transmission of millimeter-wave interconnects in noc-based multi-chip systems,” IEEE Access, 7: 112200–112215, 2019. [21] K. Duraisamy, Y. Xue, P. Bogdan, P.P. Pande, “Multicast-aware high-performance wireless network-on-chip architectures,” IEEE Trans. Very Large Scale Integr. (VLSI) Syst., 25(3): 1126–1139, 2017. [22] A. Tajary, E. Tahanian, “A routing-aware simulated annealing-based placement method in wireless network on chips,” J. AI Data Min., 8(3): 409–415, 2020. [23] W.H. Hu, C. Wang, N. Bagherzadeh, “Design and analysis of a mesh-based wireless network-on-chip,” J. Supercomput., 71(8): 2830–2846, 2015. [24] B. Bahrami, M.A. Jabraeil Jamali, S. Saeidi, “A hierarchical architecture based on traveling salesman problem for hybrid wireless network-on-chip,” Wireless Networks, 25(5): 2187–2200, 2019. [25] V. Catania, A. Mineo, S. Monteleone, M. Palesi, D. Patti, “Improving the energy efficiency of wireless network on chip architectures through online selective buffers and receivers shutdown,” in Proc. 2016 13th IEEE Annual Consumer Communications Networking Conference (CCNC): 668–673, 2016. [26] N. Jiang et al., “A detailed and flexible cycle-accurate network-on-chip simulator,” in Proc. 2013 IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS): 86–96, 2013. [27] C. Bienia, “Benchmarking modern multiprocessors,” PhD thesis, Princeton University, 2011. [28] F. Farahnakian, M. Ebrahimi, M. Daneshtalab, P. Liljeberg, J. Plosila, “Q-learning based congestion-aware routing algorithm for on-chip network,” in Proc. 2011 IEEE 2nd International Conference on Networked Embedded Systems for Enterprise Applications: 1–7, 2011. [29] F. Farahnakian, M. Ebrahimi, M. Daneshtalab, J. Plosila, P. Liljeberg, “Adaptive reinforcement learning method for networks-on-chip,” in Proc. 2012 International Conference on Embedded Computer Systems (SAMOS): 236–243, 2012. [30] J. Hestness, S.W. Keckler, “Netrace: Dependency-tracking traces for efficient network-on-chip experimentation,” The University of Texas at Austin, Department of Computer Science, 2011. [31] M. Devanathan, V. Ranganathan, P. Sivakumar, “Congestion-aware wireless network-on-chip for high-speed communication,” Automatika, 61(1): 92–98, 2020. [32] A.I. Fasiku, B.O. Ojedayo, O.E. Oyinloye, “Effect of routing algorithm on wireless network-on-chip performance,” in Proc. 2020 second international sustainability and resilience conference: Technology and innovation in building designs (51154): 1–5, 2020. [33] F. Rad, M. Reshadi, A. Khademzadeh, “A novel arbitration mechanism for crossbar switch in wireless network-on-chip,” Cluster Comput., 24(2): 1185–1198, 2021. [34] M.S. Shamim, N. Mansoor, R.S. Narde, V. Kothandapani, A. Ganguly, J. Venkataraman, “A wireless interconnection framework for seamless inter and intra-chip communication in multichip systems,” IEEE Trans. Comput., 66(3): 389–402, 2017.
آمار تعداد مشاهده مقاله: 673 تعداد دریافت فایل اصل مقاله: 615

سامانه مدیریت نشریات علمی. طراحی و پیاده سازی از سیناوب

پیوندهای مفید

آمار

An Adaptive Routing Algorithm for Wireless Network on Chips