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Karbalaei, M., Dideban, D., Moezi, N.. (1397). Improvement of Tunnel Field Effect Transistor Performance Using Auxiliary Gate and Retrograde Doping in the Channel. فناوری آموزش, 7(1), 27-33. doi: 10.22061/jecei.2019.5739.252
M. Karbalaei; D. Dideban; N. Moezi. "Improvement of Tunnel Field Effect Transistor Performance Using Auxiliary Gate and Retrograde Doping in the Channel". فناوری آموزش, 7, 1, 1397, 27-33. doi: 10.22061/jecei.2019.5739.252
Karbalaei, M., Dideban, D., Moezi, N.. (1397). 'Improvement of Tunnel Field Effect Transistor Performance Using Auxiliary Gate and Retrograde Doping in the Channel', فناوری آموزش, 7(1), pp. 27-33. doi: 10.22061/jecei.2019.5739.252
Karbalaei, M., Dideban, D., Moezi, N.. Improvement of Tunnel Field Effect Transistor Performance Using Auxiliary Gate and Retrograde Doping in the Channel. فناوری آموزش, 1397; 7(1): 27-33. doi: 10.22061/jecei.2019.5739.252

Improvement of Tunnel Field Effect Transistor Performance Using Auxiliary Gate and Retrograde Doping in the Channel

Journal of Electrical and Computer Engineering Innovations (JECEI)
مقاله 5، دوره 7، شماره 1، فروردین 2019، صفحه 27-33    اصل مقاله (975.48 K)
نوع مقاله: Original Research Paper
شناسه دیجیتال (DOI): 10.22061/jecei.2019.5739.252
نویسندگان
M. Karbalaei1؛ D. Dideban* 2؛ N. Moezi3
1Institute of nanoscience and nanotechnology, University of Kashan, Kashan, Iran.
2Department of Electrical and Computer Engineering, University of Kashan, Kashan, Iran
3Department of Electronics, Technical and Vocational University, Kashan, Iran
تاریخ دریافت: 10 اسفند 1396،  تاریخ بازنگری: 01 تیر 1397،  تاریخ پذیرش: 06 آبان 1397 
چکیده
Background and Objectives: In this work, a dual workfunction gate-source pocket-retrograde doping-tunnel field effect transistor (DWG SP RD-TFET) is proposed and investigated.
Methods: The dual workfunction gate-source pocket-retrograde doping-tunnel field effect transistor is a Silicon-channel TFET with two isolated metal gates (main gate and auxiliary gate) and a source pocket in the channel close to the source-channel junction to increase the carrier tunneling rate.
Results: For further enhancement in the tunneling rate, source doping near the source-channel junction, i.e., underneath the auxiliary gate is heavily doped to create more band bending in energy band diagram. Retrograde doping in the channel along with auxiliary gate over the source region also improve device subthreshold swing and leakage current. Based on our simulation results, excellent electrical characteristics with ION/IOFF ratio > 109, point subthreshold swing (SS) of 6 mV/dec and high gm/ID ratio at room temperature shows that this tunneling FET can be a promising device for low power applications
Conclusion: In order to increase the ON-current in this device, we utilized several methods including incorporation of high-K material in top oxide, source pocket in channel and a thin auxiliary gate with high workfunction over the source region. Incorporating auxiliary gate over the source also caused a barrier formation in the energy band diagram profile of this device which it leds electron concentration in the channel, subthreshold swing and OFF-current to be reduced.
کلیدواژه‌ها
Tunnel Field Effect Transistor (TFET)؛ Subthreshold Swing (SS)؛ Source pocket؛ Isolated gates؛ Retrograde doping
مراجع

[1] N. S. Shahraki, S. H. Zahiri, “Low-Area/Low-Power CMOS Op-Amps design based on total optimality index using reinforcement learning approach,” Journal of Electrical and Computer Engineering Innovations, 6(2): 193-208, 2018.

[2] M. Shaveisi, A. Rezaei, “Performance analysis of reversible sequential circuits based on carbon nanotube field effect transistors (CNTFETs),” Journal of Electrical and Computer Engineering Innovations, 6(2): 167-178, 2018.

[3] W. Y. Choi, H. K. Lee, “Demonstration of hetero-gate-dielectric tunneling field-effect transistors (HG TFETs),” Nano convergence, 3(13): 1-15, 2016.

[4] P. Jain, V. Prabhat, B. Ghosh, “Dual metal-double gate tunnel field effect transistor with mono/hetero dielectric gate material,” Journal of Computational Electronics, 14(2): 537-542, 2015.

[5] Y. Taur, E. J. Nowak, “CMOS devices below 0.1 /spl mu/m: how high will performance go?” in Proc. International Electron Devices Meeting. IEDM Technical Digest: 215-218, 1997.

[6] R. Jhaveri, V. Nagavarapu, and J. C. Woo, “Effect of pocket doping and annealing schemes on the source-pocket tunnel field-effect transistor,” IEEE Transactions on Electron Devices, 58(1): 80-86, 2011.

[7] C.-M. Kyung, Nano Devices and Circuit Techniques for Low-Energy Applications and Energy Harvesting, Springer, 2015.

[8] J. K. Mamidala, R. Vishnoi, P. Pandey, Tunnel Field-Effect Transistors (TFET): Modelling and Simulation, John Wiley & Sons, 2016.

[9] K. Gopalakrishnan, P. B. Griffin, J. D. Plummer, “I-MOS: A novel semiconductor device with a subthreshold slope lower than kT/q,” in Proc. Digest. International Electron Devices Meeting): 289-292, 2002.

[10] H. Kam, D. T. Lee, R. T. Howe, T.-J. King, “A new nano-electro-mechanical field effect transistor (NEMFET) design for low-power electronics,” in Proc. IEEE International Electron Devices Meeting: 463-466, 2005.

[11] G. Zhou, Y. Lu, R. Li, Q. Zhang, W. S. Hwang, Q. Liu, T. Vasen. C. Chen, H. Zhu, J.M Kuo, S. Koswatta, T. Kosel, M. Wistey, P. Fay, A. Seabaugh, H. Xing, “Vertical InGaAs/InP tunnel FETs with tunneling normal to the gate,” IEEE Electron Device Letters, 32(11): 1516-1518, 2011.

[12] D. S. Yadav, D. Sharma, B. R. Raad, V. Bajaj, “Dual workfunction hetero gate dielectric tunnel field-effect transistor performance analysis,” in Proc. International Conference on Advanced Communication Control and Computing Technologies (ICACCCT): 26-29, 2016.

[13] W. Y. Choi, W. Lee, “Hetero-gate-dielectric tunneling field-effect transistors,” IEEE Transactions on Electron Devices, 57(9): 2317-2319, 2010.

[14] M. Shirazi, A. Hassanzadeh, “Design of a low voltage low power self-biased OTA using independent gate FinFET and PTM models,” AEU-International Journal of Electronics and Communications, 82: 136-144, 2017.

[15] A. Es-Sakhi, M. Chowdhury, “Analysis of device capacitance and subthreshold behavior of Tri-gate SOI FinFET,” Microelectronics Journal, 62: 30-37, 2017.

[16] N. B. Bousari, M. K. Anvarifard, S. Haji-Nasiri, “Improving the Electrical Characteristics of Nanoscale Triple-Gate Junctionless FinFET Using Gate Oxide Engineering,” AEU-International Journal of Electronics and Communications, 108: 226-234, 2019.

[17] Q. Zhang, W. Zhao, A. Seabaugh, “Low-subthreshold-swing tunnel transistors” IEEE Electron Device Letters, 27: 297-300, 2006.

[18] W. Y. Choi, B.-G. Park, J. D. Lee, T.-J. K. Liu, “Tunneling field-effect transistors (TFETs) with subthreshold swing (SS) less than 60 mV/dec,” IEEE Electron Device Letters, 28: 743-745, 2007.

[19] F. Balestra, “Tunnel FETs for ultra low power nanoscale devices,”.

[20] J. Cao, J. Park, F. Triozon, M. G. Pala, A. Cresti, “Simulation of 2D material-based tunnel field-effect transistors: planar vs. vertical architectures,”.  

[21] Y. Lv, W. Qin, C. Wang, L. Liao, X. Liu, “Recent advances in low-dimensional heterojunction-based tunnel field effect transistors,” Advanced Electronic Materials, 5: 1-15, 2019.

[22] R. N. Sajjad, U. Radhakrishna, D. A. Antoniadis, "A tunnel FET compact model including non-idealities with verilog implementation,” Solid-State Electronics, 150: 16-22, 2018.

[23] A. Shaker, M. El Sabbagh, M. M. El-Banna, “Influence of drain doping engineering on the ambipolar conduction and high-frequency performance of TFETs,” IEEE Transactions on Electron Devices, 64: 3541-3547, 2017.

[24] S. Garg, S. Saurabh, “Suppression of ambipolar current in tunnel FETs using drain-pocket: Proposal and analysis,” Superlattices and Microstructures, 113: 261-270, 2018.

[25] K. Boucart, A. M. Ionescu, “Length scaling of the double gate tunnel FET with a high-k gate dielectric,” Solid-State Electronics, 51(11): 1500-1507, 2007.

[26] J. Knoch, S. Mantl, J. Appenzeller, “Impact of the dimensionality on the performance of tunneling FETs: Bulk versus one-dimensional devices,” Solid-State Electronics, 51(4): 572-578, 2007.

[27] S. Garg, S. Saurabh, “Improving the scalability of SOI-Based tunnel FETs using ground plane in buried oxide,” IEEE Journal of the Electron Devices Society, 7: 435-443, 2019.

[28] J.-S. Jang, W.-Y. Choi, “Ambipolarity factor of tunneling field-effect transistors (TFETs),” JSTS: Journal of Semiconductor Technology and Science, 11(4): 272-277, 2011.

[29] T. Krishnamohan, D. Kim, S. Raghunathan, K. Saraswat, “Double-Gate strained-ge heterostructure tunneling FET (TFET) with record high drive currents and ≪60mV/dec  subthreshold slope,” in Proc. IEEE International Electron Devices Meeting: 1-3, 2008.

[30] N. Dagtekin, A. M. Ionescu, “Impact of super-linear onset, off-region due to uni-directional conductance and dominant cgd on performance of TFET-based circuits,” IEEE Journal of the Electron Devices Society, 3(3): 233-239, 2014.

[31] “International Technology Roadmap for Semiconductors 2.0”.

[32] S. Saurabh, M. J. Kumar, “Impact of strain on drain current and threshold voltage of nanoscale double gate tunnel field effect transistor: Theoretical investigation and analysis,” Japanese Journal of Applied Physics, 48(6): 1-7, 2009.

[33] D. B. Abdi, M. J. Kumar, “In-built N+ pocket pnpn tunnel     field-effect transistor,” IEEE Electron Device Letters, 35(12): 1170-1172, 2014.

[34] M. Karbalaei, D. Dideban, “A novel silicon on insulator    MOSFET with an embedded heat pass path and source side channel doping,” Superlattices and Microstructures, 90): 53-67, 2016.

[35] D. S. Atlas, Atlas user’s manual. Silvaco International Software, Santa Clara, CA, USA, 2016.

[36] C. Anghel, A. Gupta, A. Amara, A. Vladimirescu, “30-nm tunnel FET with improved performance and reduced ambipolar current,” IEEE Transactions on Electron Devices, 58(6): 1649-1654, 2011.

[37] Y. Taur, T. H. Ning, Fundamentals of modern VLSI devices: Cambridge university press, 2013.

[38] J.-P. Colinge, Silicon-on-Insulator Technology: Materials to VLSI: Materials to VLSI, Springer Science & Business Media, 2004.

[39] H. L. Skriver, N. Rosengaard, “Surface energy and work   function of elemental metals,” Physical Review B, 46(11): 7157-7168, 1992.

[40] B. Dorostkar, S. Marjani, “DC analysis of pnpn tunneling field-effect transistor based on In0.35Ga0.65As,” HOLOS, 1: 288-296, 2018.

[41] H. Nam, M. H. Cho, C. Shin, “Symmetric tunnel field-effect transistor (S-TFET),” Current Applied Physics, 15(2): 71-77, 2015.

[42] K. M. Choi, W. Y. Choi, “Work-function variation effects of tunneling field-effect transistors (TFETs),” IEEE Electron Device Letters, 34(8): 942-944, 2013.

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